Bit7: Reserved.
Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag
Write: 0: CNVSTR0 is not a reset source.
1: CNVSTR0 is a reset source (active low).
Read: 0: Source of prior reset was not CNVSTR0.
1: Source of prior reset was CNVSTR0.
Bit5: C0RSEF: Comparator0 Reset Enable and Flag.
Write: 0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active low).
Read: 0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
Bit4: SWRSF: Software Reset Force and Flag.
Write: 0: No effect.
1: Forces an internal reset. /RST pin is not effected.
Read: 0: Source of last reset was not a write to the SWRSF bit.
1: Source of last reset was a write to the SWRSF bit.
Bit3: WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not WDT timeout.
1: Source of last reset was WDT timeout.
Bit2: MCDRSF: Missing Clock Detector Flag.
Write: 0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is
detected.
Read: 0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
Bit1: PORSF: Power-On Reset Flag.
Write: If the
V
DD
monitor circuitry is enabled (by tying the MONEN pin to a logic high state), this
bit can be written to select or de-select the
V
DD
monitor as a reset source.
0: De-select the
V
DD
monitor as a reset source.
1: Select the
V
DD
monitor as a reset source.
Important: At power-on, the V
DD
monitor is enabled/disabled using the external V
DD
moni-
tor enable pin (MONEN). The PORSF bit does not disable or enable the V
DD
monitor cir-
cuit. It simply selects the V
DD
monitor as a reset source.
Read: This bit is set whenever a power-on reset occurs. This may be due to a true power-on
reset or a V
DD
monitor reset. In either case, data memory should be considered indeterminate
following the reset.
0: Source of last reset was not a power-on or V
DD
monitor reset.
1: Source of last reset was a power-on or V
DD
monitor reset.
Note: When this flag is read as '1', all other reset flags are indeterminate.
Bit0: PINRSF: HW Pin Reset Flag.
Write: 0: No effect.
1: Forces a Power-On Reset. /RST is driven low.
Read: 0: Source of prior reset was not /RST pin.
1: Source of prior reset was /RST pin.
R R/W R/W R/W R R/W R R/W Reset Value
- CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF PORSF PINRSF 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xEF
0
