C8051F040/1/2/3/4/5/6/7

Rev. 1.5 157

SFR Definition 12.11. IE: Interrupt Enable

Bit7: EA: Enable All Interrupts.

This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-

tings.

0: Disable all interrupt sources.

1: Enable each interrupt according to its individual mask setting.

Bit6: IEGF0: General Purpose Flag 0.

This is a general purpose flag for use under software control.

Bit5: ET2: Enabler Timer 2 Interrupt.

This bit sets the masking of the Timer 2 interrupt.

0: Disable Timer 2 interrupt.

1: Enable interrupt requests generated by the TF2 flag.

Bit4: ES0: Enable UART0 Interrupt.

This bit sets the masking of the UART0 interrupt.

0: Disable UART0 interrupt.

1: Enable UART0 interrupt.

Bit3: ET1: Enable Timer 1 Interrupt.

This bit sets the masking of the Timer 1 interrupt.

0: Disable all Timer 1 interrupt.

1: Enable interrupt requests generated by the TF1 flag.

Bit2: EX1: Enable External Interrupt 1.

This bit sets the masking of external interrupt 1.

0: Disable external interrupt 1.

1: Enable interrupt requests generated by the /INT1 pin.

Bit1: ET0: Enable Timer 0 Interrupt.

This bit sets the masking of the Timer 0 interrupt.

0: Disable all Timer 0 interrupt.

1: Enable interrupt requests generated by the TF0 flag.

Bit0: EX0: Enable External Interrupt 0.

This bit sets the masking of external interrupt 0.

0: Disable external interrupt 0.

1: Enable interrupt requests generated by the /INT0 pin.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

EA IEGF0 ET2 ES0 ET1 EX1 ET0 EX0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xA8

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C8051F040/1/2/3/4/5/6/7

158 Rev. 1.5

SFR Definition 12.12. IP: Interrupt Priority

Bits7-6: UNUSED. Read = 11b, Write = don't care.

Bit5: PT2: Timer 2 Interrupt Priority Control.

This bit sets the priority of the Timer 2 interrupt.

0: Timer 2 interrupt priority set to low priority level.

1: Timer 2 interrupts set to high priority level.

Bit4: PS0: UART0 Interrupt Priority Control.

This bit sets the priority of the UART0 interrupt.

0: UART0 interrupt priority set to low priority level.

1: UART0 interrupts set to high priority level.

Bit3: PT1: Timer 1 Interrupt Priority Control.

This bit sets the priority of the Timer 1 interrupt.

0: Timer 1 interrupt priority set to low priority level.

1: Timer 1 interrupts set to high priority level.

Bit2: PX1: External Interrupt 1 Priority Control.

This bit sets the priority of the External Interrupt 1 interrupt.

0: External Interrupt 1 priority set to low priority level.

1: External Interrupt 1 set to high priority level.

Bit1: PT0: Timer 0 Interrupt Priority Control.

This bit sets the priority of the Timer 0 interrupt.

0: Timer 0 interrupt priority set to low priority level.

1: Timer 0 interrupt set to high priority level.

Bit0: PX0: External Interrupt 0 Priority Control.

This bit sets the priority of the External Interrupt 0 interrupt.

0: External Interrupt 0 priority set to low priority level.

1: External Interrupt 0 set to high priority level.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- - PT2 PS0 PT1 PX1 PT0 PX0 11000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xB8

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C8051F040/1/2/3/4/5/6/7

Rev. 1.5 159

SFR Definition 12.13. EIE1: Extended Interrupt Enable 1

Bit7: Reserved. Read = 0b, Write = don’t care.

Bit6: CP2IE: Enable Comparator (CP2) Interrupt.

This bit sets the masking of the CP2 interrupt.

0: Disable CP2 interrupts.

1: Enable interrupt requests generated by the CP2IF flag.

Bit6: CP1IE: Enable Comparator (CP1) Interrupt.

This bit sets the masking of the CP1 interrupt.

0: Disable CP1 interrupts.

1: Enable interrupt requests generated by the CP1IF flag.

Bit6: CP0IE: Enable Comparator (CP0) Interrupt.

This bit sets the masking of the CP0 interrupt.

0: Disable CP0 interrupts.

1: Enable interrupt requests generated by the CP0IF flag.

Bit3: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.

This bit sets the masking of the PCA0 interrupts.

0: Disable all PCA0 interrupts.

1: Enable interrupt requests generated by PCA0.

Bit2: EWADC0: Enable Window Comparison ADC0 Interrupt.

This bit sets the masking of ADC0 Window Comparison interrupt.

0: Disable ADC0 Window Comparison Interrupt.

1: Enable Interrupt requests generated by ADC0 Window Comparisons.

Bit1: ESMB0: Enable System Management Bus (SMBus0) Interrupt.

This bit sets the masking of the SMBus interrupt.

0: Disable all SMBus interrupts.

1: Enable interrupt requests generated by the SI flag.

Bit0: ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.

This bit sets the masking of SPI0 interrupt.

0: Disable all SPI0 interrupts.

1: Enable Interrupt requests generated by the SPI0 flag.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

CP2IE CP1IE CP0IE EPCA0 EWADC0 ESMB0 ESPI0 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xE6

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Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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Technical Document