C8051F040/1/2/3/4/5/6/7

148 Rev. 1.5

PCA0CPH4 0xEE 0 PCA Capture 4 High page 316

PCA0CPH5 0xE2 0 PCA Capture 5 High page 316

PCA0CPL0 0xFB 0 PCA Capture 0 Low page 316

PCA0CPL1 0xFD 0 PCA Capture 1 Low page 316

PCA0CPL2 0xE9 0 PCA Capture 2 Low page 316

PCA0CPL3 0xEB 0 PCA Capture 3 Low page 316

PCA0CPL4 0xED 0 PCA Capture 4 Low page 316

PCA0CPL5 0xE1 0 PCA Capture 5 Low page 316

PCA0CPM0 0xDA 0 PCA Module 0 Mode Register page 314

PCA0CPM1 0xDB 0 PCA Module 1 Mode Register page 314

PCA0CPM2 0xDC 0 PCA Module 2 Mode Register page 314

PCA0CPM3 0xDD 0 PCA Module 3 Mode Register page 314

PCA0CPM4 0xDE 0 PCA Module 4 Mode Register page 314

PCA0CPM5 0xDF 0 PCA Module 5 Mode Register page 314

PCA0H 0xFA 0 PCA Counter High page 315

PCA0L 0xF9 0 PCA Counter Low page 315

PCA0MD 0xD9 0 PCA Mode page 313

PCON 0x87 All Pages Power Control page 164

PSCTL 0x8F 0 Program Store R/W Control page 185

PSW 0xD0

All Pages Program Status Word page 151

RCAP2H 0xCB 0 Timer/Counter 2 Capture/Reload High page 301

RCAP2L 0xCA 0 Timer/Counter 2 Capture/Reload Low page 301

RCAP3H 0xCB 1 Timer/Counter 3 Capture/Reload High page 301

RCAP3L 0xCA 1 Timer/Counter 3 Capture/Reload Low page 301

RCAP4H 0xCB 2 Timer/Counter 4 Capture/Reload High page 301

RCAP4L 0xCA 2 Timer/Counter 4 Capture/Reload Low page 301

REF0CN 0xD1 0 Programmable Voltag

e Reference Control

page 114

, page 118

RSTSRC 0xEF 0 Reset Source Register page 170

SADDR0 0xA9 0 UART 0 Slave Address page 276

SADEN0 0xB9 0 UART 0 Slave Address Enable page 276

SBUF0 0x99 0 UART 0 Data Buffer page 276

SBUF1 0x99 1 UART 1 Data Buffer page 283

SCON0 0x98 0 UART 0 Control page 274

SCON1 0x98 1 UART 1 Control page 282

SFRPAGE 0x84 All Pages SFR Page Register page 142

SFRPGCN 0x96 F SFR Page Control Register page 142

SFRNEXT 0x85 All Pages SFR Next Page Stack Access Register page 143

SFRLAST 0x86 All Pages SFR Last Page Stack Access Register

page 143

SMB0ADR 0xC3 0 SMBus Slave Address page 250

SMB0CN 0xC0 0 SMBus Control page 247

SMB0CR 0xCF 0 SMBus Clock Rate page 248

SMB0DAT 0xC2 0 SMBus Data page 249

SMB0STA 0xC1 0 SMBus Status page 251

SP 0x81 All Pages Stack Pointer page 150

Table 12.3. Special Function Registers (Continued)

SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 149

SPI0CFG 0x9A 0 SPI Configuration page 261

SPI0CKR 0x9D 0 SPI Clock Rate Control page 263

SPI0CN 0xF8 0 SPI Control page 262

SPI0DAT 0x9B 0 SPI Data page 264

SSTA0 0x91 0 UART0 Status and Clock Selection page 275

TCON 0x88 0 Timer/Counter Control page 291

TH0 0x8C 0 Timer/Counter 0 High page 294

TH1 0x8D 0 Timer/Counter 1 High page 294

TL0 0x8A 0 Timer/Counter 0 Low page 293

TL1 0x8B 0 Timer/Counter 1 Low page 294

TMOD 0x89 0 Timer/Counter Mode page 292

TMR2CF 0xC9 0 Timer/Counter 2 Configuration page 300

TMR2CN 0xC8 0 Timer/Counter 2 Control page 299

TMR2H 0xCD 0 Timer/Counter 2 High page 302

TMR2L 0xCC 0 Timer/Counter 2 Low page 301

TMR3CF 0xC9 1 Timer/Counter 3 Configuration page 300

TMR3CN 0xC8 1 Timer 3 Control page 299

TMR3H 0xCD 1 Timer/Counter 3 High page 302

TMR3L 0xCC 1 Timer/Counter 3 Low page 301

TMR4CF 0xC9

2 Timer/Counter 4 Configuration page 300

TMR4CN 0xC8 2 Timer/Counter 4 Control page 299

TMR4H 0xCD 2 Timer/Counter 4 High page 302

TMR4L 0xCC 2 Timer/Counter 4 Low page 301

WDTCN 0xFF All Pages Watchdog Timer Control page 169

XBR0 0xE1 F Port I/O Crossbar Control 0 page 212

XBR1 0xE2 F Port I/O Crossbar Control 1 page 213

XBR2 0xE3 F Port I/O Crossbar Control 2 page 214

XBR3 0xE4 F Port I/O Crossbar Control 3 page 215

0x97, 0xA2, 0xB3, 0xB4,

0xCE, 0xDF

Reserved

Notes:

1. Re

fers to a register in the C8051F040 only.

2. Re

fers to a register in the C8051F041 only.

3. Re

fers to a register in C8051F040/1/2/3 only.

4. Re

fers to a register in the C8051F040/2/4/6 only.

5. Re

fers to a register in the C8051F041/3/5/7 only.

Table 12.3. Special Function Registers (Continued)

SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

C8051F040/1/2/3/4/5/6/7

150 Rev. 1.5

12.2.7. Register Descriptions

Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits

should not be set to logic 1. Future product versions may use these bits to implement new features, in

which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descrip-

tions of the remaining SFRs are included in the sections of the data sheet associated with their corre-

sponding system function.

SFR Definition 12.5. SP: Stack Pointer

SFR Definition 12.6. DPL: Data Pointer Low Byte

SFR Definition 12.7. DPH: Data Pointer High Byte

Bits7-0: SP: Stack Pointer.

The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented

before every PUSH operation. The SP register defaults to 0x07 after reset.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000111

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0x81

All Pages

Bits7-0: DPL: Data Pointer Low.

The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly

addressed XRAM and Flash memory.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0x82

All Pages

Bits7-0: DPH: Data Pointer High.

The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly

addressed XRAM and Flash memory.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0x83

All Pages

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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