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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
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SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
142 Rev. 1.5
SFR Definition 12.1. SFR Page Control Register: SFRPGCN
SFR Definition 12.2. SFR Page Register: SFRPAGE
Bits7-1: Reserved.
Bit0: SFRPGEN: SFR Automatic Page Control Enable.
Upon interrupt the C8051 Core will vector to the specified interrupt service routine and auto-
matically switch the SFR page to the corresponding peripheral or function’s SFR page. This
bit is used to control this autopaging function.
0: SFR Automatic Paging disabled. C8051 core will not automatically change to the appro-
priate SFR page (i.e., the SFR page that contains the SFR’s for the peripheral/function that
was the source of the interrupt).
1: SFR Automatic Paging enabled. Upon interrupt, the CIP-51 will switch the SFR page to
the page that contains the SFR’s for the peripheral or function that is the source of the inter-
rupt.
R R R R R R R R/W Reset Value
-------SFRPGEN00000001
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0x81
All Pages
Bits7-0: SFRPAGE: SFR Page Register.
Byte represents the SFR page the CIP-51 uses when reading or modifying SFR’s.
SFR page context is retained upon interrupts/return from interrupts in a 3 byte SFR Page
Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFRLAST is third entry.
The SFRPAGE, SFRSTACK, and SFRLAST bytes may be used alter the context in the SFR
Page Stack. Only interrupts and returns from interrupt service routines push and pop the
SFR Page Stack. (See Section 12.2.6.2 and Section 12.2.6.3 for further information.)
Write:
Sets the SFR Page
Read:
Byte is the SFR page the CIP-51 MCU is using.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0x84
All Pages
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 143
SFR Definition 12.3. SFR Next Register: SFRNEXT
SFR Definition 12.4. SFR Last Register: SFRLAST
Bits7-0: SFR page context is retained upon interrupts/return from interrupts in a 3 byte SFR Page
Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFRLAST is third entry.
The SFRPAGE, SFRSTACK, and SFRLAST bytes may be used alter the context in the SFR
Page Stack. Only interrupts and returns from interrupt service routines push and pop the
SFR Page Stack. (See Section 12.2.6.2 and Section 12.2.6.3 for further information.)
Write:
Sets the SFR Page contained in the second byte of the SFR Stack. This will cause the
SFRPAGE SFR to have this SFR page value upon a return from interrupt.
Read:
Returns the value of the SFR page contained in the second byte of the SFR stack. This is
the value that will go to the SFR Page register upon a return from interrupt.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0x85
All Pages
Bits7-0: SFR page context is retained upon interrupts/return from interrupts in a 3 byte SFR Page
Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFRLAST is the third
entry. The SFR stack bytes may be used alter the context in the SFR Page Stack, and will
not cause the stack to ‘push’ or ‘pop’. Only interrupts and returns from the interrupt service
routine push and pop the SFR Page Stack.
Write:
Sets the SFR Page in the last entry of the SFR Stack. This will cause the SFRNEXT SFR to
have this SFR page value upon a return from interrupt.
Read:
Returns the value of the SFR page contained in the last entry of the SFR stack.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0x86
All Pages
C8051F040/1/2/3/4/5/6/7
144 Rev. 1.5
Table 12.2. Special Function Register (SFR) Memory Map
A
D
D
R
E
S
S
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
SFR
P
A
G
E
F8
SPI0CN
CAN0CN
P7
PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL1 PCA0CPH1
WDTCN
(ALL PAGES)
0
1
2
3
F
F0
B
(ALL PAGES)
EIP1
(ALL PAGES)
EIP2
(ALL PAGES)
0
1
2
3
F
E8
ADC0CN
ADC2CN
P6
PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 PCA0CPL4 PCA0CPH4 RSTSRC
0
1
2
3
F
E0
ACC
(ALL PAGES)
PCA0CPL5
XBR0
PCA0CPH5
XBR1 XBR2 XBR3
EIE1
(ALL PAGES)
EIE2
(ALL PAGES)
0
1
2
3
F
D8
PCA0CN
CAN0DATL
P5
PCA0MD
CAN0DATH
PCA0CPM0
CAN0ADR
PCA0CPM1
CAN0TST
PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5
0
1
2
3
F
D0
PSW
(ALL PAGES)
REF0CN DAC0L
DAC1L
DAC0H
DAC1H
DAC0CN
DAC1CN
HVA0CN
0
1
2
3
F
C8
TMR2CN
TMR3CN
TMR4CN
P4
TMR2CF
TMR3CF
TMR4CF
RCAP2L
RCAP3L
RCAP4L
RCAP2H
RCAP3H
RCAP4H
TMR2L
TMR3L
TMR4L
TMR2H
TMR3H
TMR4H
SMB0CR
0
1
2
3
F
C0
SMB0CN
CAN0STA
SMB0STA SMB0DAT SMB0ADR ADC0GTL
ADC2GT
ADC0GTH ADC0LTL
ADC2LT
ADC0LTH
0
1
2
3
F
B8
IP
(ALL PAGES)
SADEN0 AMX0CF
AMX2CF
AMX0SL
AMX2SL
ADC0CF
ADC2CF
AMX0PRT ADC0L
ADC2
ADC0H
0
1
2
3
F
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
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