C8051F040/1/2/3/4/5/6/7
136 Rev. 1.5
Figure 12.3. SFR Page Stack
Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using
the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFRPGCN). This
function defaults to ‘enabled’ upon reset. In this way, the autoswitching function will be enabled unless dis-
abled in software.
A summary of the SFR locations (address and SFR page) is provided in Table 12.2. in the form of an SFR
memory map. Each memory location in the map has an SFR page row, denoting the page in which that
SFR resides. Note that certain SFR’s are accessible from ALL SFR pages, and are denoted by the “(ALL
PAGES)” designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “(ALL PAGES)”
designation, indicating these SFR’s are accessible from all SFR pages regardless of the SFRPAGE regis-
ter value.
12.2.6.3. SFR Page Stack Example
The following is an example of a C8051F040 device that sho
ws the operation of the SFR Page Stack dur-
ing interrupts.
In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the
CIP-51 is executing in-line code that is writing values to Port 5 (SFR “P5”, located at address 0xD8 on SFR
Page 0x0F). The device is also using the Programmable Counter Array (PCA) and the 8-bit ADC (ADC2)
window comparator to monitor a voltage. The PCA is timing a critical control function in its interrupt service
routine (ISR), so its interrupt is enabled and is set to high priority. The ADC2 is monitoring a voltage that is
less important, but to minimize the software overhead its window comparator is being used with an associ-
ated ISR that is set to low priority. At this point, the SFR page is set to access the Port 5 SFR (SFRPAGE =
0x0F). See Figure 12.4 below.
SFRNEXT
SFRPAGE
SFRLAST
Interrupt
Logic
