C8051F040/1/2/3/4/5/6/7
Rev. 1.5 113
9. Voltage Reference (C8051F040/2/4/6)
The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage ref-
erence input pins allow each ADC and the two DACs (C8051F040/2 only) to reference an external voltage
reference or the on-chip voltage reference output. ADC0 may also reference the DAC0 output internally,
and ADC2 may reference the analog power supply voltage, via the VREF multiplexers shown in Figure 9.1.
The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference
generator and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin
to external system components or to the voltage reference input pins shown in Figure 9.1. Bypass capaci-
tors of 0.1 µF and 4.7 µF are recommended from the VREF pin to AGND, as shown in Figure 9.1. See
Table 9.1 for voltage reference specifications.
The Reference Control Register, REF0CN (defined in SFR Definition 9.1) enables/disables the internal ref-
erence generator and selects the reference inputs for ADC0 and ADC2. The BIASE bit in REF0CN enables
the on-board reference generator while the REFBE bit enables the gain-of-two buffer amplifier which drives
the VREF pin. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less
than 1 µA (typical) and the output of the buffer amplifier enters a high impedance state. If the internal band-
gap is used as the reference voltage generator, BIASE and REFBE must both be set to logic 1. If the inter-
nal reference is not used, REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if
either DAC or ADC is used, regardless of the voltage reference used. If neither the ADC nor the DAC are
being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and AD2VRS select
the ADC0 and ADC2 voltage reference sources, respectively. The electrical specifications for the Voltage
Reference are given in Table 9.1.
The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see
Section
“5.1. Analog Multiplexer and PGA” on page 47
for C8051F040 devices, or
Section “6.1. Analog Multi-
plexer and PGA” on page 69
for C8051F042/4/6 devices). The TEMPE bit within REF0CN enables and
disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance
state and any A/D measurements performed on the sensor while disabled result in meaningless data.
Figure 9.1. Voltage Reference Functional Block Diagram
Recommended Bypass
Capacitors
x2
VREF
DAC0
DAC1
Ref
VREFD
AV+
ADC2
ADC0
VREF2
Ref
Ref
1
0
0
1
VREF0
4.7F0.1F
REF0CN
REFBE
BIASE
TEMPE
AD2VRS
AD0VRS
REFBE
BIASE
Bias to
ADCs,
DACs
1.2V
Band-Gap
EN
External
Voltage
Reference
Circuit
R1
VDD
(C8051F040/2 only)
(C8051F040/2 only)
