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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
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SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
Rev. 1.5 103
Table 7.2. ADC2 Electrical Characteristics
V
DD
= 3.0 V, AV+ = 3.0 V, V
REF2
= 2.40 V (REFBE = 0), PGA2 = 1, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 8bits
Integral Nonlinearity ——±1LSB
Differential Nonlinearity Guaranteed Monotonic ——±1LSB
Offset Error 0.5±0.3 LSB
Full Scale Error Differential mode –1±0.2 LSB
Dynamic Performance (10 kHz sine-wave input, 0 to 1 dB below Full Scale, 500 ksps)
Signal-to-Noise Plus Distortion 45 47 dB
Total Harmonic Distortion
Up to the 5
th
harmonic
—–51— dB
Spurious-Free Dynamic Range —52— dB
Conversion Rate
SAR Conversion Clock
Frequency
—— 6MHz
Conversion Time in SAR Clocks 8 clocks
Track/Hold Acquisition Time 300 ns
Throughput Rate ——500ksps
Analog Inputs
Input Voltage Range Single-ended 0 VREF V
Common Mode Range 0—AV+V
Input Capacitance —5—pF
Power Specifications
Power Supply Current
(AV+ supplied to ADC2)
Operating Mode, 500 ksps
—420900 µA
Power Supply Rejection —±0.3— mV/V
C8051F040/1/2/3/4/5/6/7
104 Rev. 1.5
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 105
8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only)
Each C8051F040/1/2/3 devices include two on-chip 12-bit voltage-mode Digital-to-Analog Converters
(DACs). Each DAC has an output swing of 0 V to (VREF – 1 LSB) for a corresponding input code range of
0x000 to 0xFFF. The DACs may be enabled/disabled via their corresponding control registers, DAC0CN
and DAC1CN. While disabled, the DAC output is maintained in a high-impedance state, and the DAC sup-
ply current falls to 1 µA or less. The voltage reference for each DAC is supplied at the VREFD pin
(C8051F040/2 devices) or the VREF pin (C8051F041/3 devices). Note that the VREF pin on C8051F041/3
devices may be driven by the internal voltage reference or an external source. If the internal voltage refer-
ence is used it must be enabled in order for the DAC outputs to be valid. See Section “9. Voltage Refer-
ence (C8051F040/2/4/6)” on page 113 or Section “10. Voltage Reference (C8051F041/3/5/7)” on
page 117 for more information on configuring the voltage reference for the DACs.
Figure 8.1. DAC Functional Block Diagram
DAC0
AV+
12
AGND
8
8
REF
DAC0
DAC0CN
DAC0EN
DAC0MD1
DAC0MD0
DAC0DF2
DAC0DF1
DAC0DF0
DAC0HDAC0L
Dig. MUX
Latch Latch
8
8
DAC1
AV+
12
AGND
8
8
REF
DAC1
DAC1CN
DAC1EN
DAC1MD1
DAC1MD0
DAC1DF2
DAC1DF1
DAC1DF0
DAC1HDAC1L
Dig. MUX
Latch Latch
8
8
DAC0H
Timer 3
Timer 4
Timer 2
DAC1H
Timer 3
Timer 4
Timer 2
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