C8051F040/1/2/3/4/5/6/7
100 Rev. 1.5
7.3. ADC2 Programmable Window Detector
The ADC2 Programmable Window Detector continuously compares the ADC2 output to user-programmed
limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an
interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response
times. The window detector interrupt flag (AD2WINT in ADC2CN) can also be used in polled mode. The
reference words are loaded into the ADC2 Greater-Than and ADC2 Less-Than registers (ADC2GT and
ADC2LT). Notice that the window detector flag can be asserted when the measured data is inside or out-
side the user-programmed limits, depending on the programming of the ADC2GT and ADC2LT registers.
SFR Definition 7.6. ADC2GT: ADC2 Greater-Than Data
SFR Definition 7.7. ADC2LT: ADC2 Less-Than Data
7.3.1. Window Detector in Single-Ended Mode
Figure 7.5 shows two example window comparisons for Single-ended mode, with ADC2LT = 0x20 and
ADC2GT = 0x10. In Single-ended mode, the codes vary from 0 to VREF x (255/256) and are represented
as 8-bit unsigned integers. In the left example, an AD2WINT interrupt will be generated if the ADC2 con-
version word (ADC2) is within the range defined by ADC2GT and ADC2LT (if 0x10 ADC2 0x20). In the
right example, and AD2WINT interrupt will be generated if ADC2 is outside of the range defined by
ADC2GT and ADC2LT (if ADC2 0x10 or ADC2 0x20).
Bits7-0: High byte of ADC2 Greater-Than Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xC4
2
Bits7-0: Low byte of ADC2 Greater-Than Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xC6
2
