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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
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SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
Rev. 1.5 97
SFR Definition 7.3. ADC2CF: ADC2 Configuration
Bits7-3: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits
SAR Conversion clock is derived from system clock by the following equation, where
AD2SC refers to the 5-bit value held in AD2SC4-0. SAR conversion clock requirements are
given in Table 7.2.
* or
*Note: AD2SC is the rounded-up result.
Bit2: UNUSED. Read = 0b. Write = don’t care.
Bits1-0: AMP2GN1-0: ADC2 Internal Amplifier Gain (PGA)
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
R/W R/W R/W R/W R/W R R/W R/W Reset Value
AD2SC4 AD2SC3 AD2SC2 AD2SC1 AD2SC0 - AMP2GN1 AMP2GN0 11111000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xBC
2
AD2SC
SYSCLK
CLK
SAR2
-----------------------
1
CLK
SAR2
SYSCLK
AD2SC 1+
----------------------------
=
C8051F040/1/2/3/4/5/6/7
98 Rev. 1.5
SFR Definition 7.4. ADC2CN: ADC2 Control
Bit7: AD2EN: ADC2 Enable Bit.
0: ADC2 Disabled. ADC2 is in low-power shutdown.
1: ADC2 Enabled. ADC2 is active and ready for data conversions.
Bit6: AD2TM: ADC2 Track Mode Bit.
0: Normal Track Mode: When ADC2 is enabled, tracking is continuous unless a conversion is in
process.
1: Low-power Track Mode: Tracking defined by AD2CM2-0 bits (see below).
Bit5: AD2INT: ADC2 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC2 has not completed a data conversion since the last time this flag was cleared.
1: ADC2 has completed a data conversion.
Bit4: AD2BUSY: ADC2 Busy Bit.
Read:
0: ADC2 Conversion is complete or a conversion is not currently in progress. AD2INT is set to
logic 1 on the falling edge of AD2BUSY.
1: ADC2 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC2 Conversion if AD2CM2-0 = 000b
Bits3-1: AD2CM2-0: ADC2 Start of Conversion Mode Select.
AD2TM = 0:
000: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY.
001: ADC2 conversion initiated on overflow of Timer 3.
010: ADC2 conversion initiated on rising edge of external CNVSTR2 or CNVSTR0.
011: ADC2 conversion initiated on overflow of Timer 2.
1xx: ADC2 conversion initiated on write of ‘1’ to AD0BUSY (synchronized with ADC0 software-
commanded conversions).
AD2TM = 1:
000: Tracking initiated on write of ‘1’ to AD2BUSY and lasts 3 SAR2 clocks, followed by conver-
sion.
001: Tracking initiated on overflow of Timer 3 and lasts 3 SAR2 clocks, followed by conversion.
010: ADC2 tracks only when CNVSTR2 (or CNVSTR0, See Section 7.2.1) input is logic low; con-
version starts on rising CNVSTR2 edge.
011: Tracking initiated on overflow of Timer 2 and lasts 3 SAR2 clocks, followed by conversion.
1xx: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR2 clocks, followed by conver-
sion.
Bit0: AD2WINT: ADC2 Window Compare Interrupt Flag.
0: ADC2 window comparison data match has not occurred since this flag was last cleared.
1: ADC2 window comparison data match has occurred. This flag must be cleared in software.
An important note about external convert start (CNVSTR0 and CNVSTR2)
: If CNVSTR2 is enabled in
the digital crossbar (
Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder”
on page 204
), CNVSTR2 will be the external convert start signal for ADC2. However, if only
CNVSTR0 is enabled in the digital crossbar and CNVSTR2 is not enabled, then CNVSTR0 may
serve as the start of conversion for both ADC0 and ADC2.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD2EN AD2TM AD2INT AD2BUSY AD2CM2 AD2CM1 AD2CM0 AD2WINT 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xE8
2
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 99
SFR Definition 7.5. ADC2: ADC2 Data Word
Figure 7.4. ADC2 Data Word Example
Bits7-0: ADC2 Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xBE
2
8-bit ADC Data Word appears in the ADC2 Data Word Register as follows:
Example: ADC2 Data Word Conversion Map, AIN1.0 Input
(AMX2SL = 0x00)
AIN1.0-AGND
(Volts)
ADC2
VREF * (255/256) 0xFF
VREF / 2 0x80
VREF * (127/256) 0x7F
0 0x00
Code Vin
Gain
VREF
---------------
256=
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