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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
Availability In Stock
Qty 2
Qty Price
1 + $20.05559
Manufacturer Available Qty
SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
94 Rev. 1.5
7.2.3. Settling Time Requirements
A minimum tracking time is required before an accurate conversion can be performed. This tracking time is
determined by the ADC2 MUX resistance, the ADC2 sampling capacitance, any external source resis-
tance, and the accuracy required for the conversion. Figure 7.3 shows the equivalent ADC2 input circuit.
The required ADC2 settling time for a given settling accuracy (SA) may be approximated by Equation 7.1.
Note: An absolute minimum settling time of 0.8 µs required after any MUX selection. Note that in low-
power tracking mode, three SAR2 clocks are used for tracking at the start of every conversion. For most
applications, these three SAR2 clocks will meet the tracking requirements.
Equation 7.1. ADC2 Settling Time Requirements
Where:
SA is the
settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the r
equired settling time in seconds
R
TOTAL
is the sum of the ADC2 MUX resistance and any external source resistance.
n is the AD
C resolution in bits (8).
Figure 7.3. ADC2 Equivalent Input Circuit
t
2
n
SA
-------


R
TOTAL
C
SAMPLE
ln=
R
MUX
= 5k
C
SAMPLE
= 10pF
RC
Input
= R
MUX
* C
SAMPLE
MUX Select
AIN2.x
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 95
SFR Definition 7.1. AMX2CF: AMUX2 Configuration
SFR Definition 7.2. AMX2SL: AMUX2 Channel Select
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bit3: PIN67IC: P1.6, P1.7 Input Pair Configuration Bit
0: P1.6 and P1.7 are independent single-ended inputs
1: P1.6, P1.7 are (respectively) +, - differential input pair
Bit2: PIN45IC: P1.4, P1.5 Input Pair Configuration Bit
0: P1.4 and P1.5 are independent single-ended inputs
1: P1.4, P1.5 are (respectively) +, - differential input pair
Bit1: PIN23IC: P1.2, P1.3 Input Pair Configuration Bit
0: P1.2 and P1.3 are independent single-ended inputs
1: P1.2, P1.3 are (respectively) +, - differential input pair
Bit0: PIN01IC: P1.0, P1.1 Input Pair Configuration Bit
0: P1.0 and P1.1 are independent single-ended inputs
1: P1.0, P1.1 are (respectively) +, - differential input pair
NOTE: The ADC2 Data Word is in 2’s complement format for channels configured as differential.
RRRRR/WR/WR/WR/WReset Value
- - - - PIN67IC PIN45IC PIN23IC PIN01IC 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xBA
2
Bits7-3: UNUSED. Read = 00000b; Write = don’t care
Bits2-0: AMX2AD2-0: AMX2 Address Bits
000-111b: ADC Inputs selected per Table 7.1.
RRRRRR/WR/WR/WReset Value
- - - - - AMX2AD2 AMX2AD1 AMX2AD0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xBB
2
C8051F040/1/2/3/4/5/6/7
96 Rev. 1.5
Table 7.1. AMUX Selection Chart (AMX2AD2-0 and AMX2CF3-0 bits)
AMX2AD2-0
000 001 010 011 100 101 110 111
AMX2CF Bits 3-0
0000
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
0001
+(P1.0)
-(P1.1)
-(P1.0)
+(P1.1)
P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
0010
P1.0 P1.1
+(P1.2)
-(P1.3)
-(P1.2)
+(P1.3)
P1.4 P1.5 P1.6 P1.7
0011
+(P1.0)
-(P1.1)
-(P1.0)
+(P1.1)
+(P1.2)
-(P1.3)
-(P1.2)
+(P1.3)
P1.4 P1.5 P1.6 P1.7
0100
P1.0 P1.1 P1.2 P1.3
+(P1.4)
-(P1.5)
-(P1.4)
+(P1.5)
P1.6 P1.7
0101
+(P1.0)
-(P1.1)
-(P1.0)
+(P1.1)
P1.2 P1.3
+(P1.4)
-(P1.5)
-(P1.4)
+(P1.5)
P1.6 P1.7
0110
P1.0 P1.1
+(P1.2)
-(P1.3)
-(P1.2)
+(P1.3)
+(P1.4)
-(P1.5)
-(P1.4)
+(P1.5)
P1.6 P1.7
0111
+(P1.0)
-(P1.1)
-(P1.0)
+(P1.1)
+(P1.2)
-(P1.3)
-(P1.2)
+(P1.3)
+(P1.4)
-(P1.5)
-(P1.4)
+(P1.5)
P1.6 P1.7
1000
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5
+(P1.6)
-(P1.7)
-(P1.6)
+(P1.7)
1001
+(P1.0)
-(P1.1)
-(P1.0)
+(P1.1)
P1.2 P1.3 P1.4 P1.5
+(P1.6)
-(P1.7)
-(P1.6)
+(P1.7)
1010
P1.0 P1.1
+(P1.2)
-(P1.3)
-(P1.2)
+(P1.3)
P1.4 P1.5
+(P1.6)
-(P1.7)
-(P1.6)
+(P1.7)
1011
+(P1.0)
-(P1.1)
-(P1.0)
+(P1.1)
+(P1.2)
-(P1.3)
-(P1.2)
+(P1.3)
P1.4 P1.5
+(P1.6)
-(P1.7)
-(P1.6)
+(P1.7)
1100
P1.0 P1.1 P1.2 P1.3
+(P1.4)
-(P1.5)
-(P1.4)
+(P1.5)
+(P1.6)
-(P1.7)
-(P1.6)
+(P1.7)
1101
+(P1.0)
-(P1.1)
-(P1.0)
+(P1.1)
P1.2 P1.3
+(P1.4)
-(P1.5)
-(P1.4)
+(P1.5)
+(P1.6)
-(P1.7)
-(P1.6)
+(P1.7)
1110
P1.0 P1.1
+(P1.2)
-(P1.3)
-(P1.2)
+(P1.3)
+(P1.4)
-(P1.5)
-(P1.4)
+(P1.5)
+(P1.6)
-(P1.7)
-(P1.6)
+(P1.7)
1111
+(P1.0)
-(P1.1)
-(P1.0)
+(P1.1)
+(P1.2)
-(P1.3)
-(P1.2)
+(P1.3)
+(P1.4)
-(P1.5)
-(P1.4)
+(P1.5)
+(P1.6)
-(P1.7)
-(P1.6)
+(P1.7)
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