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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
Availability In Stock
Qty 2
Qty Price
1 + $20.05559
Manufacturer Available Qty
SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
10 Rev. 1.5
Figure 6.5. ADC0 Equivalent Input Circuits.............................................................. 78
Figure 6.6. Temperature Sensor Transfer Function................................................. 79
Figure 6.7. ADC0 Data Word Example .................................................................... 83
Figure 6.8. 10-Bit ADC0 Window Interrupt Example:
Right Justified Single-Ended Data ........................................................ 85
Figure 6.9. 10-Bit ADC0 Window Interrupt Example:
Right Justified Differential Data............................................................. 86
Figure 6.10. 10-Bit ADC0 Window Interrupt Example:
Left Justified Single-Ended Data........................................................... 87
Figure 6.11. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data .
88
7. 8-Bit ADC (ADC2, C8051F040/1/2/3 Only)
Figure 7.1. ADC2 Functional Block Diagram............................................................ 91
Figure 7.2. ADC2 Track and Conversion Example Timing....................................... 93
Figure 7.3. ADC2 Equivalent Input Circuit................................................................ 94
Figure 7.4. ADC2 Data Word Example .................................................................... 99
Figure 7.5. ADC Window Compare Examples, Single-Ended Mode...................... 101
Figure 7.6. ADC Window Compare Examples, Differential Mode.......................... 102
8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only)
Figure 8.1. DAC Functional Block Diagram............................................................ 105
9. Voltage Reference (C8051F040/2/4/6)
Figure 9.1. Voltage Reference Functional Block Diagram ..................................... 113
10.Voltage Reference (C8051F041/3/5/7)
Figure 10.1. Voltage Reference Functional Block Diagram.................................... 117
11.Comparators
Figure 11.1. Comparator Functional Block Diagram .............................................. 121
Figure 11.2. Comparator Hysteresis Plot ............................................................... 122
12.CIP-51 Microcontroller
Figure 12.1. CIP-51 Block Diagram........................................................................ 127
Figure 12.2. Memory Map ...................................................................................... 133
Figure 12.3. SFR Page Stack................................................................................. 136
Figure 12.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5...... 137
Figure 12.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs. 138
Figure 12.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR....
139
Figure 12.7. SFR Page Stack Upon Return From PCA Interrupt ........................... 140
Figure 12.8. SFR Page Stack Upon Return From ADC2 Window Interrupt ........... 141
13.Reset Sources
Figure 13.1. Reset Sources.................................................................................... 165
Figure 13.2. Reset Timing ...................................................................................... 166
14.Oscillators
Figure 14.1. Oscillator Diagram.............................................................................. 173
Figure 14.2. 32.768 kHz External Crystal Example................................................ 177
15.Flash Memory
Figure 15.1. Flash Program Memory Map and Security Bytes............................... 181
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 11
16.External Data Memory Interface and On-Chip XRAM
Figure 16.1. Multiplexed Configuration Example.................................................... 191
Figure 16.2. Non-multiplexed Configuration Example............................................ 192
Figure 16.3. EMIF Operating Modes ...................................................................... 193
Figure 16.4. Non-multiplexed 16-bit MOVX Timing................................................ 196
Figure 16.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 197
Figure 16.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 198
Figure 16.7. Multiplexed 16-bit MOVX Timing........................................................ 199
Figure 16.8. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 200
Figure 16.9. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 201
17.Port Input/Output
Figure 17.1. Port I/O Cell Block Diagram ............................................................... 203
Figure 17.2. Port I/O Functional Block Diagram..................................................... 204
Figure 17.3. Priority Crossbar Decode Table ......................................................... 205
Figure 17.4. Priority Crossbar Decode Table ......................................................... 208
Figure 17.5. Priority Crossbar Decode Table ......................................................... 209
Figure 17.6. Crossbar Example:............................................................................. 211
18.Controller Area Network (CAN0)
Figure 18.1. Typical CAN Bus Configuration.......................................................... 227
Figure 18.2. CAN Controller Diagram..................................................................... 228
Figure 18.3. Four Segments of a CAN Bit Time..................................................... 229
Figure 18.4. CAN0DATH: CAN Data Access Register High Byte .......................... 234
19.System Management BUS/I
2
C BUS (SMBUS0)
Figure 19.1. SMBus0 Block Diagram ..................................................................... 239
Figure 19.2. Typical SMBus Configuration............................................................. 240
Figure 19.3. SMBus Transaction............................................................................ 241
Figure 19.4. Typical Master Transmitter Sequence................................................ 242
Figure 19.5. Typical Master Receiver Sequence.................................................... 243
Figure 19.6. Typical Slave Transmitter Sequence.................................................. 243
Figure 19.7. Typical Slave Receiver Sequence...................................................... 244
20.Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram ............................................................................. 255
Figure 20.2. Multiple-Master Mode Connection Diagram....................................... 258
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram............. 258
Figure 20.4. 4-Wire Single Master and Slave Mode Connection Diagram............. 258
Figure 20.5. Data/Clock Timing Diagram ............................................................... 260
21.UART0
Figure 21.1. UART0 Block Diagram ....................................................................... 265
Figure 21.2. UART0 Mode 0 Timing Diagram ........................................................ 266
Figure 21.3. UART0 Mode 0 Interconnect.............................................................. 267
Figure 21.4. UART0 Mode 1 Timing Diagram ........................................................ 267
Figure 21.5. UART0 Modes 2 and 3 Timing Diagram ............................................ 269
Figure 21.6. UART0 Modes 1, 2, and 3 Interconnect Diagram .............................. 269
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................... 272
C8051F040/1/2/3/4/5/6/7
12 Rev. 1.5
22.UART1
Figure 22.1. UART1 Block Diagram ....................................................................... 277
Figure 22.2. UART1 Baud Rate Logic.................................................................... 278
Figure 22.3. UART Interconnect Diagram .............................................................. 279
Figure 22.4. 8-Bit UART Timing Diagram............................................................... 279
Figure 22.5. 9-Bit UART Timing Diagram............................................................... 280
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 281
23.Timers
Figure 23.1. T0 Mode 0 Block Diagram.................................................................. 288
Figure 23.2. T0 Mode 2 Block Diagram.................................................................. 289
Figure 23.3. T0 Mode 3 Block Diagram.................................................................. 290
Figure 23.4. Tn Capture Mode Block Diagram....................................................... 296
Figure 23.5. Tn Auto-reload Mode and Toggle Mode Block Diagram .................... 297
24.Programmable Counter Array
Figure 24.1. PCA Block Diagram............................................................................ 303
Figure 24.2. PCA Counter/Timer Block Diagram.................................................... 304
Figure 24.3. PCA Interrupt Block Diagram ............................................................. 305
Figure 24.4. PCA Capture Mode Diagram.............................................................. 306
Figure 24.5. PCA Software Timer Mode Diagram.................................................. 307
Figure 24.6. PCA High-Speed Output Mode Diagram............................................ 308
Figure 24.7. PCA Frequency Output Mode ............................................................ 309
Figure 24.8. PCA 8-Bit PWM Mode Diagram ......................................................... 310
Figure 24.9. PCA 16-Bit PWM Mode...................................................................... 311
25.JTAG (IEEE 1149.1)
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