C8051F040/1/2/3/4/5/6/7

Rev. 1.5 79

Figure 6.6. Temperature Sensor Transfer Function

0-50 50 100

(Celsius)

0.500

0.600

0.700

0.800

0.900

(Volts)

TEMP

= 0.00286(TEMP

) + 0.776

for PGA Gain = 1

1.000

C8051F040/1/2/3/4/5/6/7

80 Rev. 1.5

SFR Definition 6.5. ADC0CF: ADC0 Configuration

Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits

SAR Conversion clock is derived from system clock by the following equation, where

AD0SC refers to the 5-bit value held in AD0SC4-0, and CLK

SAR0

refers to the desired ADC0

SAR clock. See Table 6.2 on page 89 for SAR clock setting requirements.

* or

*Note: AD0SC is the rounded-up result.

Bits2-0: AMP0GN2-0: ADC0 Internal Amplifier Gain (PGA)

000: Gain = 1

001: Gain = 2

010: Gain = 4

011: Gain = 8

10x: Gain = 16

11x: Gain = 0.5

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

SFR Page:

0xBC

AD0SC

SYSCLK

CLK

SAR0

-----------------------

1–

CLK

SAR0

SYSCLK

AD0SC 1+

----------------------------

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 81

SFR Definition 6.6. ADC0CN: ADC0 Control

Bit7: AD0EN: ADC0 Enable Bit.

0: ADC0 Disabled. ADC0 is in low-power shutdown.

1: ADC0 Enabled. ADC0 is active and ready for data conversions.

Bit6: AD0TM: ADC Track Mode Bit

0: When the ADC is enabled, tracking is continuous unless a conversion is in process

1: Tracking Defined by AD0CM1-0 bits

Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.

This flag must be cleared by software.

0: ADC0 has not completed a data conversion since the last time this flag was cleared.

1: ADC0 has completed a data conversion.

Bit4: AD0BUSY: ADC0 Busy Bit.

Read:

0: ADC0 Conversion is complete or a conversion is not currently in progress. AD0INT is set

to logic 1 on the falling edge of AD0BUSY.

1: ADC0 Conversion is in progress.

Write:

0: No Effect.

1: Initiates ADC0 Conversion if AD0CM1-0 = 00b

Bit3-2: AD0CM1-0: ADC0 Start of Conversion Mode Select.

If AD0TM = 0:

00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.

01: ADC0 conversion initiated on overflow of Timer 3.

10: ADC0 conversion initiated on rising edge of external CNVSTR0.

11: ADC0 conversion initiated on overflow of Timer 2.

If AD0TM = 1:

00: Tracking starts with the write of ‘1’ to AD0BUSY and lasts for 3 SAR clocks, followed by

conversion.

01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks, followed by con-

version.

10: ADC0 tracks only when CNVSTR0 input is logic low; conversion starts on rising

CNVSTR0 edge.

11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks, followed by con-

version.

Bit1: AD0WINT: ADC0 Window Compare Interrupt Flag.

This bit must be cleared by software.

0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.

1: ADC0 Window Comparison Data match has occurred.

Bit0: AD0LJST: ADC0 Left Justify Select.

0: Data in ADC0H:ADC0L registers are right-justified.

1: Data in ADC0H:ADC0L registers are left-justified.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 AD0WINT AD0LJST 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xE8

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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Technical Document