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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
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SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
Rev. 1.5 73
SFR Definition 6.3. AMX0PRT: Port 3 Pin Selection
Bit7: PAIN7EN: Pin 7 Analog Input Enable Bit
0: P3.7 is not selected as an analog input to the AMUX.
1: P3.7 is selected as an analog input to the AMUX.
Bit6: PAIN6EN: Pin 6 Analog Input Enable Bit
0: P3.6 is not selected as an analog input to the AMUX.
1: P3.6 is selected as an analog input to the AMUX.
Bit5: PAIN5EN: Pin 5 Analog Input Enable Bit
0: P3.5 is not selected as an analog input to the AMUX.
1: P3.5 is selected as an analog input to the AMUX.
Bit4: PAIN4EN: Pin 4 Analog Input Enable Bit
0: P3.4 is not selected as an analog input to the AMUX.
1: P3.4 is selected as an analog input to the AMUX.
Bit3: PAIN3EN: Pin 3 Analog Input Enable Bit
0: P3.3 is not selected as an analog input to the AMUX.
1: P3.3 is enabled as an analog input to the AMUX.
Bit2: PAIN2EN: Pin 2 Analog Input Enable Bit
0: P3.2 is not selected as an analog input to the AMUX.
1: P3.2 is enabled as an analog input to the AMUX.
Bit1: PAIN1EN: Pin 1 Analog Input Enable Bit
0: P3.1 is not selected as an analog input to the AMUX.
1: P3.1 is enabled as an analog input to the AMUX.
Bit0: PAIN0EN: Pin 0 Analog Input Enable Bit
0: P3.0 is not selected as an analog input to the AMUX.
1: P3.0 is enabled as an analog input to the AMUX.
NOTE: Any number of Port 3 pins may be selected simultaneously inputs to the AMUX. Odd num-
bered and even numbered pins that are selected simultaneously are shorted together as
“wired-OR”.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PAIN7EN PAIN6EN PAIN5EN PAIN4EN PAIN3EN PAIN2EN PAIN1EN PAIN0EN 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xBA
0
C8051F040/1/2/3/4/5/6/7
74 Rev. 1.5
6.2. High-Voltage Difference Amplifier
The High-Voltage Difference Amplifier (HVDA) can be used to measure high differential voltages up to
60 V peak-to-peak, reject high common-mode voltages up to ±60 V, and condition the signal voltage range
to be suitable for input to ADC0. The input signal to the HVDA may be below AGND to –60 volts, and as
high as +60 volts, making the device suitable for both single and dual supply applications. The HVDA pro-
vides a common-mode signal for the ADC via the High Voltage Reference Input (HVREF), allowing mea-
surement of signals outside the specified ADC input range using on-chip circuitry. The HVDA has a gain of
0.05 V/V to 14 V/V. The first stage 20:1 difference amplifier has a gain of 0.05 V/V when the output ampli-
fier is used as a unity gain buffer. When the output amplifier is set to a gain of 280 (selected using the
HVGAIN bits in the High Voltage Control Register), an overall gain of 14 can be attained.
The HVDA uses four available external pins: +HVAIN, –HVAIN, HVCAP, and HVREF. HVAIN+ and HVAIN-
serve as the differential inputs to the HVDA. HVREF should be used to provide a common mode reference
for input to ADC0, and to prevent the output of the HVDA circuit from saturating. The output from the
HVDA circuit as calculated by Equation 6.1 must remain within the “Output Voltage Range” specification
listed in Table 6.3. The ideal value for HVREF in most applications is equal to 1/2 the supply voltage for the
device. When the ADC is configured for differential measurement, the HVREF signal is applied to the AIN-
input of the ADC, thereby removing HVREF from the measurement. HVCAP facilitates the use of a capac-
itor for noise filtering in conjunction with R7 (see Figure 6.3 for R7 and other approximate resistor values).
Alternatively, the HVCAP could also be used to access amplification of the first stage of the HVDA at an
external pin. (See Table 6.3 on page 90 for electrical specifications of the HVDA.)
Equation 6.1. Calculating HVDA Output Voltage to AIN+
Figure 6.3. High Voltage Difference Amplifier Functional Diagram
V
OUT
HVAIN+HVAIN-Gain HVREF+=
Note: The output voltage of the HVDA is selected as an input to the AIN+ input of ADC0 via its analog multiplexer
(AMUX0). HVDA output voltages outside the ADC’s input range will result in saturation of the ADC input. Allow
for adequate settle/tracking time for proper voltage measurements.

k
5k
100k
5k
HVA0CN
Gain Setting
HVAIN-
HVAIN+
HVREF
HVCAP
Vout
(To AMUX0)
5k
Resistor values are
approximate
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 75
SFR Definition 6.4. HVA0CN: High Voltage Difference Amplifier Control
Bit7: HVDAEN: High Voltage Difference Amplifier (HVDA) Enable Bit.
0: The HVDA is disabled.
1: The HVDA is enabled.
Bits6-3: Reserved.
Bits2-0: HVGAIN3-HVGAIN0: HVDA Gain Control Bits.
HVDA Gain Control Bits set the amplification gain if the difference signal input to the HVDA
as defined in the table below:
R/W R R R R/W R/W R/W R/W Reset Value
HVDAEN - - - HVGAIN3 HVGAIN2 HVGAIN1 HVGAIN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xD6
0
HVGAIN3:HVGAIN0 HVDA Gain
0000 0.05
0001 0.1
0010 0.125
0011 0.2
0100 0.25
0101 0.4
0110 0.5
0111 0.8
1000 1.0
1001 1.6
1010 2.0
1011 3.2
1100 4.0
1101 6.2
1110 7.6
1111 14
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