C8051F040/1/2/3/4/5/6/7

Rev. 1.5 67

Table 5.2. 12-Bit ADC0 Electrical Characteristics

= 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.

Parameter Conditions Min Typ Max Units

DC Accuracy

Resolution 12 bits

Integral Nonlinearity — — ±1 LSB

Differential Nonlinearity Guaranteed Monotonic — — ±1 LSB

Offset Error Note 1 — 0.5±3 — LSB

Full Scale Error Differential mode; See Note 1 — 0.4±3 — LSB

Offset Temperature Coefficient — ±0.25 — ppm/°C

Dynamic Performance (10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps)

Signal-to-Noise Plus Distortion 66 — — dB

Total Harmonic Distortion

Up to the 5

harmonic

— –75 — dB

Spurious-Free Dynamic Range — 80 — dB

Conversion Rate

Maximum SAR Clock Frequency — — 2.5 MHz

Conversion Time in SAR Clocks 16 — — clocks

Track/Hold Acquisition Time 1.5 — — µs

Throughput Rate — — 100 ksps

Analog Inputs

Input Voltage Range Single-ended operation 0 — VREF V

Common-mode Voltage Range Differential operation AGND — AV+ V

Input Capacitance — 10 — pF

Temperature Sensor

Nonlinearity Notes 1, 2 — ±1 — °C

Absolute Accuracy Notes 1, 2 — ±3 — °C

Gain Notes 1, 2 —

2.86

±0.034

— mV/°C

Offset Notes 1, 2 (Temp = 0 °C) —

0.776

±0.009

— V

Power Specifications

Power Supply Current (AV+ sup-

plied to ADC)

Operating Mode, 100 ksps — 450 900 µA

Power Supply Rejection — ±0.3 — mV/V

Notes:

1. Re

presents one standard deviation from the mean.

2. Inclu

des ADC offset, gain, and linearity variations.

C8051F040/1/2/3/4/5/6/7

68 Rev. 1.5

Table 5.3. High-Voltage Difference Amplifier Electrical Characteristics

= 3.0 V, AV+ = 3.0 V, V

REF

= 3.0 V, –40 to +85 °C unless otherwise specified.

Parameter Conditions Min Typ Max Units

Analog Inputs

Differential range peak-to-peak ——60 V

Common Mode Range (HVAIN+) – (HVAIN–) = 0 V –60 — +60 V

Analog Output

Output Voltage Range 0.1 — 2.9 V

DC Performance

Common Mode Rejection Ratio Vcm= –10 V to +10 V, Rs=0 44 52 — dB

Offset Voltage —±3— mV

Noise HVCAP floating —500—nV/rtHz

Nonlinearity G = 1 —72— dB

Dynamic Performance

Small Signal Bandwidth G = 0.05 —3— MHz

Small Signal Bandwidth G = 1 —150— kHz

Slew Rate —2— V/µs

Settling Time 0.01%, G = 0.05, 10 V step —10— µs

Input/Output Impedance

Differential (HVAIN+) input —105— k

Differential (HV

AIN-) input —98— k

Common Mode input —51— k

HVCAP —5— k

Power Specification

Quiescent Current — 450 1000 µA

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 69

6. 10-Bit ADC (ADC0, C8051F042/3/4/5/6/7 Only)

The ADC0 subsystem for the C8051F042/3/4/5/6/7 consists of a 9-channel, configurable analog multi-

plexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approxima-

tion-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram

in Figure 6.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable

under software control via the Special Function Registers shown in Figure 6.1. The voltage reference used

by ADC0 is selected as described in Section “9. Voltage Reference (C8051F040/2/4/6)” on page 113 for

C8051F042/4/6 devices, or Section “10. Voltage Reference (C8051F041/3/5/7)” on page 117 for

C8051F043/5/7 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when

the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low

power shutdown when this bit is logic 0.

Figure 6.1. 10-Bit ADC0 Functional Block Diagram

6.1. Analog Multiplexer and PGA

The analog multiplexer can input analog signals to the ADC from four external analog input pins, Port 3

port pins (optionally configured as analog input pins), High Voltage Difference Amplifier, and an internally

connected on-chip temperature sensor (temperature transfer function is shown in Figure 6.6). AMUX input

pairs can be programmed to operate in either differential or single-ended mode. This allows the user to

select the best measurement technique for each input channel, and even accommodates mode changes

"on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are three registers associated

with the AMUX: the Channel Selection register AMX0SL (SFR Definition 6.2), the Configuration register

AMX0CF (SFR Definition 6.1), and the Port Pin Selection register AMX0PRT (SFR Definition 6.3).

Table 6.1 shows AMUX functionality by channel for each possible configuration. The PGA amplifies the

AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configu-

ration register, ADC0CF (SFR Definition 6.5). The PGA can be software-programmed for gains of 0.5, 2, 4,

8 or 16. Gain defaults to unity on reset.

10-Bit

SAR

ADC

REF

AV+

TEMP

SENSOR

9-to-1

AMUX

(SE or

DIFF)

AV+

AD0EN

SYSCLK

Start Conversion

AGND

AMX0CF

ADC0L ADC0H

ADC0LTLADC0LTHADC0GTLADC0GTH

AMX0SL

AMX0AD0

AMX0AD1

AMX0AD2

AMX0AD3

AIN01IC

AIN23IC

HVDA2IC

PORT3IC

ADC0CF

AMP0GN0

AMP0GN1

AMP0GN2

AD0SC0

AD0SC1

AD0SC2

AD0SC3

AD0SC4

ADC0CN

AD0LJST

AD0WINT

AD0CM0

AD0CM1

AD0BUSY

AD0INT

AD0TM

AD0EN

Timer 3 Overflow

AD0BUSY (W)

CNVSTR0

AD0WINT

Comb.

Logic

Input

Port 3

I/O Pins

Analog

Input

Pins

AGND Timer 2 Overflow

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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