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C8051F041-GQ

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

Qty	Price
1 +	$20.05559

Manufacturer	Available	Qty
SILICON LABORATORIES Date Code: 0903	Freelance Stock: 2 Ships Immediately

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Technical Document

DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7

64 Rev. 1.5

Figure 5.9. 12-Bit ADC0 Window Interrupt Example:

Right Justified Differential Data

0x07FF

0x0101

0x0100

0x00FF

0x0000

0xFFFF

0xFFFE

0xF800

AD0WINT=1

AD0WINT

not affected

AD0WINT

not affected

0x07FF

0x0101

0x0100

0x00FF

0x0000

0xFFFF

0xFFFE

0xF800

AD0WINT=1

AD0WINT

not affected

-REF

Input Voltage

(AD0 - AD1)

AD0WINT=1

REF x (2047/2048)

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC Data

Word

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

REF x (256/2048)

REF x (-1/2048)

-REF

Input Voltage

(AD0 - AD1)

REF x (2047/2048)

REF x (256/2048)

REF x (-1/2048)

Given:

AMX0SL = 0x00, AMX0CF = 0x01,

AD0LJST = ‘0’,

ADC0LTH:ADC0LTL = 0x0100,

ADC0GTH:ADC0GTL = 0xFFFF.

An ADC0 End of Conversion will cause an

ADC0 Window Compare Interrupt (AD0WINT

= ‘1’) if the resulting ADC0 Data Word is

< 0x0100 and > 0xFFFF. (In two’s-complement

math, 0xFFFF = -1.)

Given:

AMX0SL = 0x00, AMX0CF = 0x01,

AD0LJST = ‘0’,

ADC0LTH:ADC0LTL = 0xFFFF,

ADC0GTH:ADC0GTL = 0x0100.

An ADC0 End of Conversion will cause an

ADC0 Window Compare Interrupt (AD0WINT

= ‘1’) if the resulting ADC0 Data Word is

< 0xFFFF or > 0x0100. (In two’s-complement

math, 0xFFFF = -1.)

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 65

Figure 5.10. 12-Bit ADC0 Window Interrupt Example:

Left Justified Single-Ended Data

0xFFF0

0x2010

0x2000

0x1FF0

0x1010

0x1000

0x0FF0

0x0000

AD0WINT=1

AD0WINT

not affected

AD0WINT

not affected

ADC Data

Word

0xFFF0

0x2010

0x2000

0x1FF0

0x1010

0x1000

0x0FF0

0x0000

AD0WINT=1

AD0WINT

not affected

AD0WINT=1

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC0GTH:ADC0GTL

ADC0LTH:ADC0LTL

0

Input Voltage

(AD0 - AGND)

REF x (4095/4096)

REF x (256/4096)

REF x (512/4096)

0

Input Voltage

(AD0 - AGND)

REF x (4095/4096)

REF x (256/4096)

REF x (512/4096)

Given:

AMX0SL = 0x00, AMX0CF = 0x00,

AD0LJST = ‘1’,

ADC0LTH:ADC0LTL = 0x2000,

ADC0GTH:ADC0GTL = 0x1000.

An ADC0 End of Conversion will cause an

ADC0 Window Compare Interrupt (AD0WINT

= ‘1’) if the resulting ADC0 Data Word is

< 0x2000 and > 0x1000.

Given:

AMX0SL = 0x00, AMX0CF = 0x00,

AD0LJST = ‘1’

ADC0LTH:ADC0LTL = 0x1000,

ADC0GTH:ADC0GTL = 0x2000.

An ADC0 End of Conversion will cause an

ADC0 Window Compare Interrupt (AD0WINT

= ‘1’) if the resulting ADC0 Data Word is

< 0x1000 or > 0x2000.

C8051F040/1/2/3/4/5/6/7

66 Rev. 1.5

Figure 5.11. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data

0x7FF0

0x1010

0x1000

0x0FF0

0x0000

0xFFF0

0xFFE0

0x8000

AD0WINT=1

AD0WINT

not affected

AD0WINT

not affected

0x7FF0

0x1010

0x1000

0x0FF0

0x0000

0xFFF0

0xFFE0

0x8000

AD0WINT=1

AD0WINT

not affected

-REF

Input Voltage

(AD0 - AD1)

AD0WINT=1

REF x (2047/2048)

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC Data

Word

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

REF x (256/2048)

REF x (-1/2048)

-REF

Input Voltage

(AD0 - AD1)

REF x (2047/2048)

REF x (256/2048)

REF x (-1/2048)

Given:

AMX0SL = 0x00, AMX0CF = 0x01,

AD0LJST = ‘1’,

ADC0LTH:ADC0LTL = 0x1000,

ADC0GTH:ADC0GTL = 0xFFF0.

An ADC0 End of Conversion will cause an

ADC0 Window Compare Interrupt (AD0WINT

= ‘1’) if the resulting ADC0 Data Word is

< 0x1000 and > 0xFFF0. (Two’s-complement

math.)

Given:

AMX0SL = 0x00, AMX0CF = 0x01,

AD0LJST = ‘1’,

ADC0LTH:ADC0LTL = 0xFFF0,

ADC0GTH:ADC0GTL = 0x1000.

An ADC0 End of Conversion will cause an

ADC0 Window Compare Interrupt (AD0WINT

= ‘1’) if the resulting ADC0 Data Word is

< 0xFFF0 or > 0x1000. (Two’s-complement

math.)

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