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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
Availability In Stock
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SILICON LABORATORIES
Date Code: 0903
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
Rev. 1.5 49
SFR Definition 5.1. AMX0CF: AMUX0 Configuration
SFR Definition 5.2. AMX0SL: AMUX0 Channel Select
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bit3: PORT3IC: Port 3 even/odd Pin Input Pair Configuration Bit
0: Port 3 even and odd input channels are independent single-ended inputs
1: Port 3 even and odd input channels are (respectively) +, - difference input pair
Bit2: HVDA2C: HVDA 2’s Compliment Bit
0: HVDA output measured as an independent single-ended input
1: HVDA result for 2’s compliment value
Bit1: AIN23IC: AIN0.2, AIN0.3 Input Pair Configuration Bit
0: AIN0.2 and AIN0.3 are independent single-ended inputs
1: AIN0.2, AIN0.3 are (respectively) +, - difference input pair
Bit0: AIN01IC: AIN0.0, AIN0.1 Input Pair Configuration Bit
0: AIN0.0 and AIN0.1 are independent single-ended inputs
1: AIN0.0, AIN0.1 are (respectively) +, - difference input pair
NOTE: The ADC0 Data Word is in 2’s complement format for channels configured as difference.
R R R R R/W R/W R/W R/W Reset Value
- - - - PORT3IC HVDA2C AIN23IC AIN01IC 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR
Address:
SFR Address:
SFR Page:
0xBA
0
Bits7-4: UNUSED. Read = 0000b; Write = don’t care
Bits3-0: AMX0AD3-0: AMX0 Address Bits
0000-1111b: ADC Inputs selected per Table 5.1.
R R R R R/W R/W R/W R/W Reset Value
- - - - AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xBB
0
C8051F040/1/2/3/4/5/6/7
50 Rev. 1.5
Note: “P3EVEN” denotes even numbered and “P3ODD” odd numbered Port 3 pins selected in the AMX0PRT
register.
Table 5.1. AMUX Selection Chart (AMX0AD3–0 and AMX0CF3–0 bits)
AMX0AD3-0
0000 0001 0010 0011 0100 0101 0110 0111 1xxx
AMX0CF Bits 3-0
0000
AIN0.0 AIN0.1 AIN0.2 AIN0.3 HVDA AGND P3EVEN P3ODD
TEMP
SENSO
R
0001
+(AIN0.0)
-(AIN0.1)
AIN0.2 AIN0.3 HVDA AGND P3EVEN P3ODD
TEMP
SENSO
R
0010
AIN0.0 AIN0.1
+(AIN0.2)
-(AIN0.3)
HVDA AGND P3EVEN P3ODD
TEMP
SENSO
R
0011
+(AIN0.0)
-(AIN0.1)
+(AIN0.2)
-(AIN0.3)
HVDA AGND P3EVEN P3ODD
TEMP
SENSOR
0100
AIN0.0 AIN0.1 AIN0.2 AIN0.3
+(HVDA)
-(HVREF)
P3EVEN P3ODD
TEMP
SENSO
R
0101
+(AIN0.0)
-(AIN0.1)
AIN0.2 AIN0.3
+(HVDA)
-(HVREF)
P3EVEN P3ODD
TEMP
SENSOR
0110
AIN0.0 AIN0.1
+(AIN0.2)
-(AIN0.3)
+(HVDA)
-(HVREF)
P3EVEN P3ODD
TEMP
SENSO
R
0111
+(AIN0.0)
-(AIN0.1)
+(AIN0.2)
-(AIN0.3)
+(HVDA)
-(HVREF)
P3EVEN P3ODD
TEMP
SENSO
R
1000
AIN0.0 AIN0.1 AIN0.2 AIN0.3 HVDA AGND
+P3EVEN
-P3ODD
TEMP
SENSO
R
1001
+(AIN0.0)
-(AIN0.1)
AIN0.2 AIN0.3 HVDA AGND
+P3EVEN
-P3ODD
TEMP
SENSO
R
1010
AIN0.0 AIN0.1
+(AIN0.2)
-(AIN0.3)
HVDA AGND
+P3EVEN
-P3ODD
TEMP
SENSO
R
1011
+(AIN0.0)
-(AIN0.1)
+(AIN0.2)
-(AIN0.3)
HVDA AGND
+P3EVEN
-P3ODD
TEMP
SENSO
R
1100
AIN0.0 AIN0.1 AIN0.2 AIN0.3
+(HVDA)
-(HVREF)
+P3EVEN
-P3ODD)
TEMP
SENSO
R
1101
+(AIN0.0)
-(AIN0.1)
AIN0.2 AIN0.3
+(HVDA)
-(HVREF)
+P3EVEN
-P3ODD
TEMP
SENSOR
1110
AIN0.0 AIN0.1
+(AIN0.2)
-(AIN0.3)
+(HVDA)
-(HVREF)
+P3EVEN
-P3ODD
TEMP
SENSO
R
1111
+(AIN0.0)
-(AIN0.1)
+(AIN0.2)
-(AIN0.3)
+(HVDA)
-(HVREF)
+P3EVEN
-P3ODD
TEMP
SENSOR
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 51
SFR Definition 5.3. AMX0PRT: Port 3 Pin Selection
Bit7: PAIN7EN: Pin 7 Analog Input Enable Bit
0: P3.7 is not selected as an analog input to the AMUX.
1: P3.7 is selected as an analog input to the AMUX.
Bit6: PAIN6EN: Pin 6 Analog Input Enable Bit
0: P3.6 is not selected as an analog input to the AMUX.
1: P3.6 is selected as an analog input to the AMUX.
Bit5: PAIN5EN: Pin 5 Analog Input Enable Bit
0: P3.5 is not selected as an analog input to the AMUX.
1: P3.5 is selected as an analog input to the AMUX.
Bit4: PAIN4EN: Pin 4 Analog Input Enable Bit
0: P3.4 is not selected as an analog input to the AMUX.
1: P3.4 is selected as an analog input to the AMUX.
Bit3: PAIN3EN: Pin 3 Analog Input Enable Bit
0: P3.3 is not selected as an analog input to the AMUX.
1: P3.3 is enabled as an analog input to the AMUX.
Bit2: PAIN2EN: Pin 2 Analog Input Enable Bit
0: P3.2 is not selected as an analog input to the AMUX.
1: P3.2 is enabled as an analog input to the AMUX.
Bit1: PAIN1EN: Pin 1 Analog Input Enable Bit
0: P3.1 is not selected as an analog input to the AMUX.
1: P3.1 is enabled as an analog input to the AMUX.
Bit0: PAIN0EN: Pin 0 Analog Input Enable Bit
0: P3.0 is not selected as an analog input to the AMUX.
1: P3.0 is enabled as an analog input to the AMUX.
Note:Any number of Port 3 pins may be selected simultaneously inputs to the AMUX. Odd numbered and even
numbered pins that are selected simultaneously are shorted together as “wired-OR”.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PAIN7EN PAIN6EN PAIN5EN PAIN4EN PAIN3EN PAIN2EN PAIN1EN PAIN0EN 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page:
0xBD
0
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