Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968

We Stock Hard to Find Parts
My Account | My Orders | My Cart
Questions? (800) 300-1968

C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
Availability In Stock
Qty 2
Qty Price
1 + $20.05559
Manufacturer Available Qty
SILICON LABORATORIES
Date Code: 0903
  • Shipping Freelance Stock: 2
    Ships Immediately

Related Items

C8051F061-GQ
SILICON LABORATORIES
IC
C8051F061-GQ
$11.61022
C8051F321-GMR
SILICON LABS
IC
C8051F321-GMR
$10.41286
008-25424
Fairchild Semiconductor
IC
008-25424
$11.58351
01-6945-9
Harris Corporation
IC
01-6945-9
 
010-143121-0002
Motorola Corp
IC
010-143121-0002
 
01295-672141D
Texas Instruments
IC
01295-672141D
 


Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
Rev. 1.5 37
4. Pinout and Package Definitions
Table 4.1. Pin Definitions
Name
Pin Numbers
Type Description
F040/2/4/6 F041/3/5/7
V
DD
37, 64, 90 24, 41, 57 Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
DGND 38, 63, 89 25, 40, 56 Digital Ground. Must be tied
to Ground.
AV+ 8, 11, 14 3, 6 Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.
AGND 9, 10, 13 4, 5 Analog Ground. Must be tied to Ground.
TMS 1 58 D In JTAG Test Mode Select with internal pullup.
TCK 2 59 D In JTAG Test Clock with internal pullup.
TDI 3 60 D In JTAG Test Data Input with internal pullup. TDI
is latched
on the rising edge of TCK.
TDO 4 61 D Out JTAG Test Data Output with internal pullup. Data is
shif
ted out on TDO on the falling edge of TCK. TDO out-
put is a tri-state driver.
/RST 5 62 D I/O Device Reset. Open-drain outpu
t of internal V
DD
monitor.
Is driven low when V
DD
is < 2.7 V and MONEN is high. An
external source can initiate a system reset by driving this
pin low.
XTAL1 26 17 A In Crystal Input. This pin is the return for the internal
oscilla-
tor circuit for a crystal or ceramic resonator. For a preci-
sion internal clock, connect a
crystal or ceramic resonator
from XTAL1 to XTAL2. If overdriven by an external CMOS
clock, this becomes the system clock.
XTAL2 27 18 A Out Crystal Output. This pin is the excitation driver for a crystal
or ceramic
resonator.
MONEN 28 19 D In V
DD
Monitor Enable. When tied high, this pin enables the
internal V
DD
monitor, which forces a system reset when
V
DD
is < 2.7 V. When tied low, the internal V
DD
monitor is
disabled.
In most applications, MONEN should be connected
di
rectly to V
DD
.
VREF 12 7 A I/O Bandgap Voltage Reference Output (all devices).
DAC Voltage Reference Input (C8051F041/3 only).
VREFA 8 A In ADC0 (C8051F041/3/5/7) and ADC2 (C8051F041/3 only)
Voltage Reference Input.
VREF0 16 A In ADC0 Voltage Reference Input.
VREF2 17 A In ADC2 Voltage Reference Input (C8051F040/2 only).
VREF 15 A In DAC Voltage Reference Input (C8051F040/2 only).
AIN0.0 18 9 A In ADC0 Input Channel 0 (See ADC0 Specification for com-
plete description).
C8051F040/1/2/3/4/5/6/7
38 Rev. 1.5
AIN0.1 19 10 A In ADC0 Input Channel 1 (See ADC0 Specification for com-
plete description).
AIN0.2 20 11 A In ADC0 Input Channel 2 (See ADC0 Specification for com-
plete description).
AIN0.3 21 12 A In ADC0 Input Channel 3 (See ADC0 Specification for com-
plete description).
HVCAP 22 13 A I/O High Voltage Difference Amplifier Capacitor.
HVREF 23 14 A In High Voltage Difference Amplifier Bias Reference.
HVAIN+ 24 15 A In High Voltage Difference Amplifier Positive Signal
Input.
HVAIN- 25 16 A In High Voltage Difference Amplifie
r Negative Signal Input.
CANTX 7 2 D Out Controller Area Network Transmit Output.
CANRX 6 1 D In Controller Area Network Receive Input.
DAC0 100 64 A Out Digital to Analog Converter 0 Voltage Output. (See DAC
S
pecification for complete description). (C8051F040/1/2/3
only)
DAC1 99 63 A Out Digital to Analog Converter 1 Voltage Output. (See DAC
S
pecification for complete description). (C8051F040/1/2/3
only)
P0.0 62 55 D I/O Port 0.0. See Port Input/Output section for complete
de
scription.
P0.1 61 54 D I/O Port 0.1. See Port Input/Output section for complete
de
scription.
P0.2 60 53 D I/O Port 0.2. See Port Input/Output section for complete
de
scription.
P0.3 59 52 D I/O Port 0.3. See Port Input/Output section for complete
de
scription.
P0.4 58 51 D I/O Port 0.4. See Port Input/Output section for complete
de
scription.
P0.5/ALE 57 50 D I/O ALE Strobe for External Memory Address bus (multi-
plexed mode) Port 0.5
See Port Input/Output section for complete description.
P0.6/RD 56 49 D I/O /RD Strobe for External Memory Address bus
Port 0.6
See Port Input/Output section for complete description.
P0.7/WR 55 48 D I/O /WR Strobe for External Memory Address bus
Port 0.7
See Port Input/Output section for complete description.
Table 4.1. Pin Definitions (Continued)
Name
Pin Numbers
Type Description
F040/2/4/6 F041/3/5/7
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 39
P1.0/AIN2.0/A8 36 29 A In
D I/O
ADC1 Input Channel 0 (See ADC1 Specification for com-
plete description).
Bit 8 External Memory Address bus (Non-multiplexed
mo
de)
Port 1.0
See Port Input/Output section for complete description.
P1.1/AIN2.1/A9 35 28 A In
D I/O
Port 1.1. See Port Input/Output section for complete
de
scription.
P1.2/AIN2.2/
A10
34 27 A In
D I/O
Port 1.2. See Port Input/Output section for complete
de
scription.
P1.3/AIN2.3/
A1
1
33 26 A In
D I/O
Port 1.3. See Port Input/Output section for complete
description.
P1.4/AIN2.4/
A12
32 23 A In
D I/O
Port 1.4. See Port Input/Output section for complete
de
scription.
P1.5/AIN2.5/
A13
31 22 A In
D I/O
Port 1.5. See Port Input/Output section for complete
de
scription.
P1.6/AIN2.6/
A14
30 21 A In
D I/O
Port 1.6. See Port Input/Output section for complete
de
scription.
P1.7/AIN2.7/
A15
29 20 A In
D I/O
Port 1.7. See Port Input/Output section for complete
de
scription.
P2.0/A8m/A0 46 37 D I/O Bit 8 External Memory Address bus (Multiplexed mode)
Bit 0 External Memory Address bus (Non-multiplexed
mo
de) Port 2.0
See Port Input/Output section for complete description.
P2.1/A9m/A1 45 36 D I/O Port 2.1. See Port Input/Output section for complete
de
scription.
P2.2/A10m/A2 44 35 D I/O Port 2.2. See Port Input/Output section for complete
de
scription.
P2.3/A11m/A3 43 34 D I/O Port 2.3. See Port Input/Output section for complete
de
scription.
P2.4/A12m/A4 42 33 D I/O Port 2.4. See Port Input/Output section for complete
de
scription.
P2.5/A13m/A5 41 32 D I/O Port 2.5. See Port Input/Output section for complete
de
scription.
P2.6/A14m/A6 40 31 D I/O Port 2.6. See Port Input/Output section for complete
de
scription.
P2.7/A15m/A7 39 30 D I/O Port 2.7. See Port Input/Output section for complete
de
scription.
Table 4.1. Pin Definitions (Continued)
Name
Pin Numbers
Type Description
F040/2/4/6 F041/3/5/7
PREVIOUS678910111213141516171819NEXT
Address
Freelance Electronics
13197 Sandoval Street
Santa Fe Springs, CA 90670
 
Hours of Operation  (Holiday Hours)
Monday-Friday 7:30am-4:30pm PST
(Deadline for next day shipment 2:00pm PST)
Seal
Government Cage code#-1V4R6
Duns Number# 788130532
Certified Small Disadvantaged Business
Customer Service
Company
Information
Connect with Us
Twitter Facebook Instagra,
This site is protected by Trustwave's Trusted Commerce program