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C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
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SILICON LABORATORIES
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
34 Rev. 1.5
1.10. Comparators and DACs
Each C8051F040/1/2/3 MCU has two 12-bit DACs, and all C8051F04x devices have three comparators on
chip. The MCU data and control interface to each comparator and DAC is via the Special Function Regis-
ters. The MCU can place any DAC or comparator in low power shutdown mode.
The comparators have software programmable hysteresis and response time. Each comparator can gen-
erate an interrupt on its rising edge, falling edge, or both; these interrupts are capable of waking up the
MCU from sleep mode. The comparators' output state can also be polled in software. The comparator out-
puts can be programmed to appear on the Port I/O pins via the Crossbar.
The DACs are voltage output mode and include a flexible output scheduling mechanism. This scheduling
mechanism allows DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The
DAC voltage reference is supplied via the dedicated VREFD input pin on C8051F040/2 devices or via the
internal voltage reference on C8051F041/3 devices. The DACs are especially useful as references for the
comparators or offsets for the differential inputs of the ADC.
Figure 1.14. Comparator and DAC Diagram
+
-
CPn+
CPn-
DAC0
DAC1
VREF
VREF
CIP-51
and
Interrupt
Handler
CPn
DAC0
DAC1
CPn Output
(Port I/O)
SFR's
(Data
and
Cntrl)
CROSSBAR
3 Comparators
Comparator inputs
Port 2.[7:2]
(C8051F040/1/2/3 only)
(C8051F040/1/2/3 only)
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 35
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 125 °C
Storage Temperature –65 150 °C
Voltage on any Pin (except V
DD
, Port I/O, and JTAG
pins) with respect to DGND
–0.3 V
DD
+
0.3
V
Voltage on any Port I/O Pin, /RST, and JTAG pins with
respect to DGND
–0.3 5.8 V
Voltage on V
DD
with respect to DGND –0.3 4.2 V
Maximum Total current through V
DD
, AV+, DGND,
and AGND
——800mA
Maximum output current sunk by any Port pin 100 mA
Maximum output current sunk by any other I/O pin 50 mA
Maximum output current sourced by any Port pin 100 mA
Maximum output current sourced by any other I/O pin 50 mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Due to special I/O design requirements of the High Voltage Dif
ference Amplifier, undue electrical over-voltage
stress (i.e., ESD) experienced by these pads may result in impedance degradation of these inputs (HVAIN+
and HVAIN–). For this reason, care should be taken to ensure proper handling and use as typically required to
prevent ESD damage to electrostatically sensitive CMOS devices (e.g., static-free workstations, use of
grounding straps, over-voltage protection in end-applications, etc.)
C8051F040/1/2/3/4/5/6/7
36 Rev. 1.5
3. Global DC Electrical Characteristic
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Analog Supply Voltage
1
2.7 3.0 3.6 V
Analog Supply Current Internal REF, ADC, DAC, Com-
parators all active
—1.7—mA
Analog Supply Current with
analog sub-systems inactive
Internal REF, ADC, DAC, Com-
parators all disabled, oscillator
disabled
—0.2—µA
Analog-to-Digital Supply
Delta (|V
DD
- AV+|)
——0.5V
Digital Supply Voltage 2.7 3.0 3.6 V
Digital Supply Current with
CPU active
(Normal Mode)
V
DD
= 2.7 V, Clock = 25 MHz
V
DD
= 2.7 V, Clock = 1 MHz
V
DD
= 2.7 V, Clock = 32 kHz
10
0.5
20
mA
mA
µA
Digital Supply Current with
CPU inactive (not accessing
Flash) (Idle Mode)
V
DD
= 2.7 V, Clock = 25 MHz
V
DD
= 2.7 V, Clock = 1 MHz
V
DD
= 2.7 V, Clock = 32 kHz
5
0.2
10
mA
mA
µA
Digital Supply Current
(shutdown) (Stop Mode)
Oscillator not running 0.2 µA
Digital Supply RAM Data
Retention Voltage
—1.5— V
Specified Operating
Temperature Range
–40 +85 °C
SYSCLK (system clock
frequency)
2
0—25MHz
Tsysl (SYSCLK low time) 18 ns
Tsysh (SYSCLK high time) 18 ns
Notes:
1. Anal
og Supply AV+ must be greater than 1 V for V
DD
monitor to operate.
2. SYSCLK m
ust be at least 32 kHz to enable debugging.
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