C8051F040/1/2/3/4/5/6/7

Rev. 1.5 299

SFR Definition 23.8. TMRnCN: Timer n Control

Bit7: TFn: Timer n Overflow/Underflow Flag.

Set by hardware when either the Timer overflows from 0xFFFF to 0x0000, underflows from

the value placed in RCAPnH:RCAPnL to 0xFFFF (in Auto-reload Mode), or underflows from

0x0000 to 0xFFFF (in Capture Mode). When the Timer interrupt is enabled, setting this bit

causes the CPU to vector to the Timer interrupt service routine. This bit is not automatically

cleared by hardware and must be cleared by software.

Bit6: EXFn: Timer 2, 3, or 4 External Flag.

Set by hardware when either a capture or reload is caused by a high-to-low transition on the

TnEX input pin and EXENn is logic 1. When the Timer interrupt is enabled, setting this bit

causes the CPU to vector to the Timer Interrupt service routine. This bit is not automatically

cleared by hardware and must be cleared by software.

Bit5-4: Reserved.

Bit3: EXENn: Timer n External Enable.

Enables high-to-low transitions on TnEX to trigger captures, reloads, and control the direc-

tion of the timer/counter (up or down count). If DECEN = 1, TnEX will determine if the timer

counts up or down when in Auto-reload Mode. If EXENn = 1, TnEX should be configured as

a digital input.

0: Transitions on the TnEX pin are ignored.

1: Transitions on the TnEX pin cause capture, reload, or control the direction of timer count

(up or down) as follows:

Capture Mode

: ‘1’-to-’0’ Transition on TnEX pin causes RCAPnH:RCAPnL to capture timer

value.

Auto-Reload Mode

DCEN = 0: ‘1’-to-’0’ transition causes reload of timer and sets the EXFn Flag.

DCEN = 1: TnEX logic level controls direction of timer (up or down).

Bit2: TRn: Timer n Run Control.

This bit enables/disables the respective Timer.

0: Timer disabled.

1: Timer enabled and running/counting.

Bit1: C/Tn: Counter/Timer Select.

0: Timer Function: Timer incremented by clock defined by TnM1:TnM0

(TMRnCF.4:TMRnCF.3).

1: Counter Function: Timer incremented by high-to-low transitions on external input pin.

Bit0: CP/RLn: Capture/Reload Select.

This bit selects whether the Timer functions in capture or auto-reload mode.

0: Timer is in Auto-Reload Mode.

1: Timer is in Capture Mode.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

TFn EXFn - - EXENn TRn C/Tn CP/RLn 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit

Addressable

SFR Address: TMR2CN:0xC8;TMR3CN:0xC8;TMR4CN:0xC8

SFR Page: TMR2CN: page 0;TMR3CN: page 1;TMR4CN: page 2

C8051F040/1/2/3/4/5/6/7

300 Rev. 1.5

SFR Definition 23.9. TMRnCF: Timer n Configuration

Bit7-5: Reserved.

Bit4-3: TnM1 and TnM0: Timer Clock Mode Select Bits.

Bits used to select the Timer clock source. The sources can be the System Clock

(SYSCLK), SYSCLK divided by 2 or 12, or an external clock signal routed to Tn (port pin)

divided by 8. Clock source is selected as follows:

00: SYSCLK/12

01: SYSCLK

10: EXTERNAL CLOCK/8

11: SYSCLK/2

Bit2: TOGn: Toggle output state bit.

When timer is used to toggle a port pin, this bit can be used to read the state of the output, or

can be written to in order to force the state of the output.

Bit1: TnOE: Timer output enable bit.

This bit enables the timer to output a 50% duty cycle output to the timer’s assigned external

port pin.

NOTE

: A timer is configured for Square Wave Output as follows:

CP/RLn= 0

C/Tn = 0

TnOE = 1

Load RCAPnH:RCAPnL (See Section “Equation 23.1. Square Wave Frequency” on

page 298).

Configure Port Pin for output (See Section “17. Port Input/Output” on page 203).

0: Output of toggle mode not available at Timers’ assigned port pin.

1: Output of toggle mode available at Timers’ assigned port pin.

Bit0: DCEN: Decrement Enable Bit.

This bit enables the timer to count up or down as determined by the state of TnEX.

0: Timer will count up, regardless of the state of TnEX.

1: Timer will count up or down depending on the state of TnEX as follows:

if TnEX = 0, the timer counts DOWN

if TnEX = 1, the timer counts UP.

R/W R/W R/W R/W R/W Reset Value

- - - TnM1 TnM0 TOGn TnOE DCEN 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit

Addressable

SFR Address: TMR2CF:0xC9;TMR3CF:0xC9;TMR4CF:0xC9

SFR Page TMR2CF: page 0;TMR3CF: page 1;TMR4CF: page 2

C8051F040/1/2/3/4/5/6/7

Rev. 1.5 301

SFR Definition 23.10. RCAPnL: Timer n Capture Register Low Byte

SFR Definition 23.11. RCAPnH: Timer n Capture Register High Byte

SFR Definition 23.12. TMRnL: Timer n Low Byte

Bits 7-0: RCAPnL: Timer n Capture Register Low Byte.

The RCAPnL register captures the low byte of Timer n when Timer n is configured in capture

mode. When Timer n is configured in auto-reload mode, it holds the low byte of the reload

value.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address: RCAP2L: 0xCA; RCAP3L: 0xCA; RCAP4L: 0xCA

SFR Page: RCAP2L: page 0; RCAP3L: page 1; RCAP4L: page 2

Bits 7-0: RCAPnH: Timer n Capture Register High Byte.

The RCAPnH register captures the high byte of Timer n when Timer n is configured in cap-

ture mode. When Timer n is configured in auto-reload mode, it holds the high byte of the

reload value.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address: RCAP2H: 0xCB; RCAP3H: 0xCB; RCAP4H: 0xCB

SFR Page: RCAP2H: page 0; RCAP3H: page 1; RCAP4H: page 2

Bits 7-0: TMRnL: Timer n Low Byte.

The TMRnL register contains the low byte of the 16-bit Timer n

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address: TMR2L: 0xCC; TMR3L: 0xCC; TMR4L: 0xCC

SFR Page: TMR2L: page 0; TMR3L: page 1; TMR4L: page 2

Part #	C8051F041-GQ
Description	MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category	IC
Availability	In Stock
Qty	2

C8051F041-GQ

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