C8051F040/1/2/3/4/5/6/7
32 Rev. 1.5
1.8. 12/10-Bit Analog to Digital Converter
The C8051F040/1 devices have an on-chip 12-bit SAR ADC (ADC0) with a 9-channel input multiplexer
and programmable gain amplifier. With a maximum throughput of 100 ksps, the ADC offers true 12-bit per-
formance with an INL of ±1LSB. C8051F042/3/4/5/6/7 devices include a 10-bit SAR ADC with similar spec-
ifications and configuration options. The ADC0 voltage reference is selected between the DAC0 output
and an external VREF pin. On C8051F040/2/4/6 devices, ADC0 has its own dedicated VREF0 input pin;
on C8051F041/3/5/7 devices, the ADC0 uses the VREFA input pin and, on the C8051F041/3, shares it
with the 8-bit ADC2. The on-chip 15 ppm/°C voltage reference may generate the voltage reference for the
on-chip ADCs or other system components via the VREF output pin.
The ADC is under full control of the CIP-51 microcontroller via its associated Special Function Registers.
One input channel is tied to an internal temperature sensor, while the other eight channels are available
externally. Each pair of the eight external input channels can be configured as either two single-ended
inputs or a single differential input. The system controller can also put the ADC into shutdown mode to
save power.
A programmable gain amplifier follows the analog multiplexer. The gain can be set to 0.5, 1, 2, 4, 8, or 16
and is software programmable. The gain stage can be especially useful when different ADC input channels
have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large dc
offset (in differential mode, a DAC could be used to provide the dc offset).
Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of
Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by software
events, external HW signals, or a periodic timer overflow signal. Conversion completions are indicated by a
status bit and an interrupt (if enabled). The resulting 10- or 12-bit data word is latched into two SFRs upon
completion of a conversion. The data can be right or left justified in these registers under software control.
Window Compare registers for the ADC data can be configured to interrupt the controller when ADC data
is within or outside of a specified range. The ADC can monitor a key voltage continuously in background
mode, but not interrupt the controller unless the converted data is within the specified window.
Figure 1.12. 10/12-Bit ADC Block Diagram
12/10-Bit
SAR
ADC
12
+
-
TEMP
SENSOR
+
-
+
-
9-to-1
AMUX
(SE or
DIFF)
+
-
X
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AV+
Programmable Gain
Amplifier
Analog Multiplexer
Window Compare
Logic
ADC Data
Registers
Window
Compare
Interrupt
Conversion
Complete
Interrupt
Configuration, Control, and Data
Registers
Start
Conversion
Timer 3 Overflow
Timer 2 Overflow
Write to AD0BUSY
CNVSTR0
External VREF
Pin
DAC0 Output
(C8051F040/1/2/3 Only)
VREF
AGND
HVDA
HVAIN +
HVAIN -
Port 3
Pins
