Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968

We Stock Hard to Find Parts
My Account | My Orders | My Cart
Questions? (800) 300-1968

C8051F041-GQ

Part # C8051F041-GQ
Description MCU 8BIT CISC 64KB FLASH 3V 64TQFP - Trays
Category IC
Availability In Stock
Qty 2
Qty Price
1 + $20.05559
Manufacturer Available Qty
SILICON LABORATORIES
Date Code: 0903
  • Shipping Freelance Stock: 2
    Ships Immediately

Related Items

C8051F061-GQ
SILICON LABORATORIES
IC
C8051F061-GQ
$11.61022
C8051F321-GMR
SILICON LABS
IC
C8051F321-GMR
$10.41286
008-25424
Fairchild Semiconductor
IC
008-25424
$11.58351
01-6945-9
Harris Corporation
IC
01-6945-9
 
010-143121-0002
Motorola Corp
IC
010-143121-0002
 
01295-672141D
Texas Instruments
IC
01295-672141D
 


Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

C8051F040/1/2/3/4/5/6/7
4 Rev. 1.5
7.3.2. Window Detector in Differential Mode.................................................... 102
8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only) ......................................... 105
8.1. DAC Output Scheduling.................................................................................. 106
8.1.1. Update Output On-Demand ................................................................... 106
8.1.2. Update Output Based on Timer Overflow .............................................. 106
8.2. DAC Output Scaling/Justification.................................................................... 106
9. Voltage Reference (C8051F040/2/4/6)................................................................. 113
10.Voltage Reference (C8051F041/3/5/7)................................................................. 117
11.Comparators......................................................................................................... 121
11.1.Comparator Inputs.......................................................................................... 123
12.CIP-51 Microcontroller......................................................................................... 127
12.1.Instruction Set................................................................................................. 129
12.1.1.Instruction and CPU Timing ................................................................... 129
12.1.2.MOVX Instruction and Program Memory ............................................... 129
12.2.Memory Organization ..................................................................................... 133
12.2.1.Program Memory ................................................................................... 133
12.2.2.Data Memory.......................................................................................... 134
12.2.3.General Purpose Registers.................................................................... 134
12.2.4.Bit Addressable Locations...................................................................... 134
12.2.5.Stack ..................................................................................................... 134
12.2.6.Special Function Registers .................................................................... 135
12.2.7.Register Descriptions............................................................................. 150
12.3.Interrupt Handler............................................................................................. 153
12.3.1.MCU Interrupt Sources and Vectors ...................................................... 153
12.3.2.External Interrupts.................................................................................. 154
12.3.3.Interrupt Priorities................................................................................... 156
12.3.4.Interrupt Latency .................................................................................... 156
12.3.5.Interrupt Register Descriptions............................................................... 156
12.4.Power Management Modes............................................................................ 163
12.4.1.Idle Mode ............................................................................................... 163
12.4.2.Stop Mode.............................................................................................. 164
13.Reset Sources....................................................................................................... 165
13.1.Power-On Reset............................................................................................. 166
13.2.Power-Fail Reset............................................................................................
166
13.3.External Reset................................................................................................ 166
13.4.Missing Clock Detector Reset ........................................................................ 167
13.5.Comparator0 Reset ........................................................................................ 167
13.6.External CNVSTR0 Pin Reset........................................................................ 167
13.7.Watchdog Timer Reset................................................................................... 167
13.7.1.Enable/Reset WDT ................................................................................ 168
13.7.2.Disable WDT.......................................................................................... 168
13.7.3.Disable WDT Lockout ............................................................................ 168
13.7.4.Setting WDT Interval.............................................................................. 168
14.Oscillators............................................................................................................. 173
14.1.Programmable Internal Oscillator................................................................... 173
C8051F040/1/2/3/4/5/6/7
Rev. 1.5 5
14.2.External Oscillator Drive Circuit...................................................................... 175
14.3.System Clock Selection.................................................................................. 175
14.4.External Crystal Example ............................................................................... 177
14.5.External RC Example ..................................................................................... 178
14.6.External Capacitor Example........................................................................... 178
15.Flash Memory ....................................................................................................... 179
15.1.Programming The Flash Memory................................................................... 179
15.2.Non-volatile Data Storage .............................................................................. 180
15.3.Security Options ............................................................................................. 180
15.3.1.Summary of Flash Security Options....................................................... 183
16.External Data Memory Interface and On-Chip XRAM........................................ 187
16.1.Accessing XRAM............................................................................................ 187
16.1.1.16-Bit MOVX Example ........................................................................... 187
16.1.2.8-Bit MOVX Example ............................................................................. 187
16.2.Configuring the External Memory Interface.................................................... 188
16.3.Port Selection and Configuration.................................................................... 188
16.4.Multiplexed and Non-multiplexed Selection.................................................... 191
16.4.1.Multiplexed Configuration....................................................................... 191
16.4.2.Non-multiplexed Configuration............................................................... 192
16.5.Memory Mode Selection................................................................................. 193
16.5.1.Internal XRAM Only ............................................................................... 193
16.5.2.Split Mode without Bank Select.............................................................. 193
16.5.3.Split Mode with Bank Select................................................................... 194
16.5.4.External Only.......................................................................................... 194
16.6.Timing .......................................................................................................... 194
16.6.1.Non-multiplexed Mode ........................................................................... 196
16.6.2.Multiplexed Mode................................................................................... 199
17.Port Input/Output.................................................................................................. 203
17.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 204
17.1.1.Crossbar Pin Assignment and Allocation............................................... 205
17.1.2.Configuring the Output Modes of the Port Pins...................................... 206
17.1.3.Configuring Port Pins as Digital Inputs................................................... 206
17.1.4.Weak Pullups ......................................................................................... 207
17.1.5.Configuring Port 1, 2, and 3 Pins as Analog Inputs ............................... 207
17.1.6.External Memory Interface Pin Assignments
......................................... 208
17.1.7.Crossbar Pin Assignment Example........................................................ 210
17.2.Ports 4 through 7............................................................................................ 220
17.2.1.Configuring Ports Which are Not Pinned Out......................................... 221
17.2.2.Configuring the Output Modes of the Port Pins...................................... 221
17.2.3.Configuring Port Pins as Digital Inputs................................................... 221
17.2.4.Weak Pullups ......................................................................................... 221
17.2.5.External Memory Interface..................................................................... 221
18.Controller Area Network (CAN0)......................................................................... 227
18.1.Bosch CAN Controller Operation.................................................................... 228
18.1.1.CAN Controller Timing ........................................................................... 229
C8051F040/1/2/3/4/5/6/7
6 Rev. 1.5
18.1.2.Example Timing Calculation for 1 Mbit/Sec Communication ................. 229
18.2.CAN Registers................................................................................................ 231
18.2.1.CAN Controller Protocol Registers......................................................... 231
18.2.2.Message Object Interface Registers...................................................... 231
18.2.3.Message Handler Registers................................................................... 232
18.2.4.CIP-51 MCU Special Function Registers............................................... 232
18.2.5.Using CAN0ADR, CAN0DATH, and CANDATL to Access CAN Registers .
232
18.2.6.CAN0ADR Autoincrement Feature ........................................................ 232
19.System Management BUS/I
2
C BUS (SMBUS0).................................................. 239
19.1.Supporting Documents................................................................................... 240
19.2.SMBus Protocol.............................................................................................. 241
19.2.1.Arbitration............................................................................................... 241
19.2.2.Clock Low Extension.............................................................................. 242
19.2.3.SCL Low Timeout................................................................................... 242
19.2.4.SCL High (SMBus Free) Timeout .......................................................... 242
19.3.SMBus Transfer Modes.................................................................................. 242
19.3.1.Master Transmitter Mode....................................................................... 242
19.3.2.Master Receiver Mode........................................................................... 243
19.3.3.Slave Transmitter Mode......................................................................... 243
19.3.4.Slave Receiver Mode............................................................................. 244
19.4.SMBus Special Function Registers ................................................................ 245
19.4.1.Control Register ..................................................................................... 245
19.4.2.Clock Rate Register ............................................................................... 248
19.4.3.Data Register ......................................................................................... 249
19.4.4.Address Register.................................................................................... 249
19.4.5.Status Register....................................................................................... 250
20.Enhanced Serial Peripheral Interface (SPI0)...................................................... 255
20.1.Signal Descriptions......................................................................................... 256
20.1.1.Master Out, Slave In (MOSI).................................................................. 256
20.1.2.Master In, Slave Out (MISO).................................................................. 256
20.1.3.Serial Clock (SCK) ................................................................................. 256
20.1.4.Slave Select (NSS) ................................................................................ 256
20.2.SPI0 Master Mode Operation......................................................................... 257
20.3.SPI0 Slave Mode Operation........................................................................... 259
20.4.SPI0 Interrupt Sources ................................................................................... 259
20.5.Serial Clock Timing......................................................................................... 260
20.6.SPI Special Function Registers...................................................................... 261
21.UART0.................................................................................................................... 265
21.1.UART0 Operational Modes ............................................................................ 266
21.1.1.Mode 0: Synchronous Mode .................................................................. 266
21.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 267
21.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate .................................................. 269
21.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 270
21.2.Multiprocessor Communications ....................................................................
270
PREVIOUS12345678NEXT
Address
Freelance Electronics
13197 Sandoval Street
Santa Fe Springs, CA 90670
 
Hours of Operation  (Holiday Hours)
Monday-Friday 7:30am-4:30pm PST
(Deadline for next day shipment 2:00pm PST)
Seal
Government Cage code#-1V4R6
Duns Number# 788130532
Certified Small Disadvantaged Business
Customer Service
Company
Information
Connect with Us
Twitter Facebook Instagra,
This site is protected by Trustwave's Trusted Commerce program