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Wait_ee:

sbic EECR, EEPE

rjmp Wait_ee

; SPM timed sequence

out SPMCSR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

25.3 Register Description

25.3.1 SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Program memory operations.

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-

PRGEN bit in the SPMCSR Register is cleared. The interrupt will not be generated during

EEPROM write or SPM.

• Bit 6 – RWWSB: Read-While-Write Section Busy

This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero

in ATmega48.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega48/88/168 and will always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

The functionality of this bit in ATmega48 is a subset of the functionality in ATmega88/168. If the

RWWSRE bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

The functionality of this bit in ATmega48 is a subset of the functionality in ATmega88/168. An

LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR

destination register. See “Reading the Fuse and Lock Bits from Software” on page 265 for

details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Write, with the data stored in the temporary buffer. The page

address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The

Bit 7 6 5 4 3 2 1 0

0x37 (0x57)

SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS

SELFPRGEN

SPMCSR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed

within four clock cycles. The CPU is halted during the entire Page Write operation.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Erase. The page address is taken from the high part of the Z-

pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a

Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-

ing the entire Page Write operation.

• Bit 0 – SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a spe-

cial meaning, see description above. If only SELFPRGEN is written, the following SPM

instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.

The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an

SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase

and Page Write, the SELFPRGEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

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26. Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and

ATmega168

26.1 Features

• Read-While-Write Self-Programming

• Flexible Boot Memory Size

• High Security (Separate Boot Lock Bits for a Flexible Protection)

• Separate Fuse to Select Reset Vector

• Optimized Page

(1)

Size

• Code Efficient Algorithm

• Efficient Read-Modify-Write Support

Note: 1. A page is a section in the Flash consisting of several bytes (see Table 27-9 on page 290) used

during programming. The page organization does not affect normal operation.

26.2 Overview

In ATmega88 and ATmega168, the Boot Loader Support provides a real Read-While-Write Self-

Programming mechanism for downloading and uploading program code by the MCU itself. This

feature allows flexible application software updates controlled by the MCU using a Flash-resi-

dent Boot Loader program. The Boot Loader program can use any available data interface and

associated protocol to read code and write (program) that code into the Flash memory, or read

the code from the program memory. The program code within the Boot Loader section has the

capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can

thus even modify itself, and it can also erase itself from the code if the feature is not needed any-

more. The size of the Boot Loader memory is configurable with fuses and the Boot Loader has

two separate sets of Boot Lock bits which can be set independently. This gives the user a

unique flexibility to select different levels of protection.

26.3 Application and Boot Loader Flash Sections

The Flash memory is organized in two main sections, the Application section and the Boot

Loader section (see Figure 26-2). The size of the different sections is configured by the

BOOTSZ Fuses as shown in Table 26-6 on page 282 and Figure 26-2. These two sections can

have different level of protection since they have different sets of Lock bits.

26.3.1 Application Section

The Application section is the section of the Flash that is used for storing the application code.

The protection level for the Application section can be selected by the application Boot Lock bits

(Boot Lock bits 0), see Table 26-2 on page 274. The Application section can never store any

Boot Loader code since the SPM instruction is disabled when executed from the Application

section.

26.3.2 BLS – Boot Loader Section

While the Application section is used for storing the application code, the The Boot Loader soft-

ware must be located in the BLS since the SPM instruction can initiate a programming when

executing from the BLS only. The SPM instruction can access the entire Flash, including the

BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader

Lock bits (Boot Lock bits 1), see Table 26-3 on page 274.

Part #	ATMEGA48-20AU
Description	MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category	IC
Availability	Out of Stock
Qty	0

ATMEGA48-20AU

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