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Figure 21-18. Formats and States in the Slave Transmitter Mode

21.7.5 Miscellaneous States

There are two status codes that do not correspond to a defined TWI state, see Table 21-6.

Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not

set. This occurs between other states, and when the TWI is not involved in a serial transfer.

Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus

error occurs when a START or STOP condition occurs at an illegal position in the format frame.

Examples of such illegal positions are during the serial transfer of an address byte, a data byte,

or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the

TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the

TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in

TWCR are affected). The SDA and SCL lines are released, and no STOP condition is

transmitted.

21.7.6 Combining Several TWI Modes

In some cases, several TWI modes must be combined in order to complete the desired action.

Consider for example reading data from a serial EEPROM. Typically, such a transfer involves

the following steps:

1. The transfer must be initiated.

2. The EEPROM must be instructed what location should be read.

3. The reading must be performed.

4. The transfer must be finished.

S SLA R A DATA A

$A8 $B8

$B0

Reception of the own

slave address and one or

more data bytes

Last data byte transmitted.

Switched to not addressed

slave (TWEA = '0')

Arbitration lost as master

and addressed as slave

From master to slave

From slave to master

Any number of data bytes

and their associated acknowledge bits

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

prescaler bits are zero or masked to zero

P or SDATA

$C0

DATA A

$C8

P or SAll 1's

Table 21-6. Miscellaneous States

Status Code

(TWSR)

Prescaler Bits

are 0

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR

To TWCR

STA STO TWIN

TWE

0xF8 No relevant state information

available; TWINT = “0”

No TWDR action No TWCR action Wait or proceed current transfer

0x00 Bus error due to an illegal

START or STOP condition

No TWDR action 0 1 1 X Only the internal hardware is affected, no STOP condi-

tion is sent on the bus. In all cases, the bus is released

and TWSTO is cleared.

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Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct

the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data

must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must

be changed. The Master must keep control of the bus during all these steps, and the steps

should be carried out as an atomical operation. If this principle is violated in a multi master sys-

tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the

Master will read the wrong data location. Such a change in transfer direction is accomplished by

transmitting a REPEATED START between the transmission of the address byte and reception

of the data. After a REPEATED START, the Master keeps ownership of the bus. The following

figure shows the flow in this transfer.

Figure 21-19. Combining Several TWI Modes to Access a Serial EEPROM

21.8 Multi-master Systems and Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simulta-

neously by one or more of them. The TWI standard ensures that such situations are handled in

such a way that one of the masters will be allowed to proceed with the transfer, and that no data

will be lost in the process. An example of an arbitration situation is depicted below, where two

masters are trying to transmit data to a Slave Receiver.

Figure 21-20. An Arbitration Example

Several different scenarios may arise during arbitration, as described below:

• Two or more masters are performing identical communication with the same Slave. In this

case, neither the Slave nor any of the masters will know about the bus contention.

• Two or more masters are accessing the same Slave with different data or direction bit. In this

case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying

to output a one on SDA while another Master outputs a zero will lose the arbitration. Losing

masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new

START condition, depending on application software action.

Master Transmitter Master Receiver

S = START Rs = REPEATED START P = STOP

Transmitted from master to slave Transmitted from slave to master

S SLA+W A ADDRESS A Rs SLA+R A DATA A P

Device 1

MASTER

TRANSMITTER

Device 2

MASTER

TRANSMITTER

Device 3

SLAVE

RECEIVER

Device n

SDA

SCL

........

R1 R2

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• Two or more masters are accessing different slaves. In this case, arbitration will occur in the

SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose

the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are

being addressed by the winning Master. If addressed, they will switch to SR or ST mode,

depending on the value of the READ/WRITE bit. If they are not being addressed, they will

switch to not addressed Slave mode or wait until the bus is free and transmit a new START

condition, depending on application software action.

This is summarized in Figure 21-21. Possible status values are given in circles.

Figure 21-21. Possible Status Codes Caused by Arbitration

21.9 Register Description

21.9.1 TWBR – TWI Bit Rate Register

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency

divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator

Unit” on page 217 for calculating bit rates.

21.9.2 TWCR – TWI Control Register

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a

Master access by applying a START condition to the bus, to generate a Receiver acknowledge,

to generate a stop condition, and to control halting of the bus while the data to be written to the

bus are written to the TWDR. It also indicates a write collision if data is attempted written to

TWDR while the register is inaccessible.

Own

Address / General Call

received

Arbitration lost in SLA

TWI bus will be released and not addressed slave mode will be entered

A START condition will be transmitted when the bus becomes free

Arbitration lost in Data

Direction

Ye s

Write

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be returned

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

Read

68/78

SLASTART Data STOP

Bit 76543210

(0xB8) TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0xBC) TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE TWCR

Read/Write R/W R/W R/W R/W R R/W R R/W

Initial Value 0 0 0 0 0 0 0 0

Part #	ATMEGA48-20AU
Description	MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category	IC
Availability	Out of Stock
Qty	0

ATMEGA48-20AU

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