226

2545M–AVR–09/07

ATmega48/88/168

Figure 21-12. Formats and States in the Master Transmitter Mode

21.7.2 Master Receiver Mode

In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter

(Slave see Figure 21-13). In order to enter a Master mode, a START condition must be transmit-

ted. The format of the following address packet determines whether Master Transmitter or

Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R

is transmitted, MR mode is entered. All the status codes mentioned in this section assume that

the prescaler bits are zero or are masked to zero.

S SLA W A DATA A P

$08

$18 $28

R SLA W

$10

$20

$30

A or A

$38

Other master

continues

A or A

$38

Other master

continues

$68

Other master

continues

$78 $B0

To corresponding

states in slave mode

Successfull

transmission

to a slave

receiver

Next transfer

started with a

repeated start

condition

Not acknowledge

received after the

slave address

Not acknowledge

received after a data

byte

Arbitration lost in slave

address or data byte

Arbitration lost and

addressed as slave

DATA A

From master to slave

From slave to master

Any number of data bytes

and their associated acknowledge bits

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

rescaler bits are zero or masked to zero

227

2545M–AVR–09/07

ATmega48/88/168

Figure 21-13. Data Transfer in Master Receiver Mode

A START condition is sent by writing the following value to TWCR:

TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to

one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI

will then test the 2-wire Serial Bus and generate a START condition as soon as the bus

becomes free. After a START condition has been transmitted, the TWINT Flag is set by hard-

ware, and the status code in TWSR will be 0x08 (See Table 21-2). In order to enter MR mode,

SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit

should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing

the following value to TWCR:

When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes

is detailed in Table 21-3. Received data can be read from the TWDR Register when the TWINT

Flag is set high by hardware. This scheme is repeated until the last byte has been received.

After the last byte has been received, the MR should inform the ST by sending a NACK after the

last received data byte. The transfer is ended by generating a STOP condition or a repeated

START condition. A STOP condition is generated by writing the following value to TWCR:

A REPEATED START condition is generated by writing the following value to TWCR:

After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same

Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE

value 1

X10X10 X

TWCR TWINT

TWEA TWSTA TWSTO TWWC TWEN – TWIE

value 1

X00X10 X

TWCR TWINT

TWEA TWSTA TWSTO TWWC TWEN – TWIE

value 1

X01X10 X

TWCR TWINT

TWEA TWSTA TWSTO TWWC TWEN – TWIE

value 1

X10X10 X

Device 1

MASTER

RECEIVER

Device 2

SLAVE

TRANSMITTER

Device 3

Device n

SDA

SCL

........

R1 R2

228

2545M–AVR–09/07

ATmega48/88/168

the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-

out losing control over the bus.

Table 21-3. Status codes for Master Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR

To TWCR

STA STO TWIN

TWE

0x08 A START condition has been

transmitted

Load SLA+R 0 0 1 X SLA+R will be transmitted

ACK or NOT ACK will be received

0x10 A repeated START condition

has been transmitted

Load SLA+R or

Load SLA+W

SLA+R will be transmitted

ACK or NOT ACK will be received

SLA+W will be transmitted

Logic will switch to Master Transmitter mode

0x38 Arbitration lost in SLA+R or

NOT ACK bit

No TWDR action or

No TWDR action

2-wire Serial Bus will be released and not addressed

Slave mode will be entered

A START condition will be transmitted when the bus

becomes free

0x40 SLA+R has been transmitted;

ACK has been received

No TWDR action or

No TWDR action

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x48 SLA+R has been transmitted;

NOT ACK has been received

No TWDR action or

No TWDR action

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO Flag

will be reset

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

0x50 Data byte has been received;

ACK has been returned

Read data byte or

Read data byte

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x58 Data byte has been received;

NOT ACK has been returned

Read data byte or

Read data byte

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO Flag

will be reset

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

Part #	ATMEGA48-20AU
Description	MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category	IC
Availability	Out of Stock
Qty	0

ATMEGA48-20AU

Related Items

Technical Document