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ATMEGA48-20AU

Part # ATMEGA48-20AU
Description MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

193
2545M–AVR–09/07
ATmega48/88/168
Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to
zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
19.10.4 UCSRnC – USART Control and Status Register n C
Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in Table 19-4.
Note: 1. See “USART in SPI Mode” on page 200 for full description of the Master SPI Mode (MSPIM)
operation
Bit 7 6 5 4 3 2 1 0
UMSELn1 UMSELn0 UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn UCSRnC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 1 1 0
Table 19-4. UMSELn Bits Settings
UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 (Reserved)
1 1 Master SPI (MSPIM)
(1)
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Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 19-5. UPMn Bits Settings
UPMn1 UPMn0 Parity Mode
00Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 19-6. USBS Bit Settings
USBSn Stop Bit(s)
01-bit
12-bit
Table 19-7. UCSZn Bits Settings
UCSZn2 UCSZn1 UCSZn0 Character Size
0005-bit
0016-bit
0107-bit
0118-bit
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1119-bit
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ATmega48/88/168
19.10.5 UBRRnL and UBRRnH – USART Baud Rate Registers
Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRnH is written.
Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four
most significant bits, and the UBRRnL contains the eight least significant bits of the USART
baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud
rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.
19.11 Examples of Baud Rate Setting
For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-
chronous operation can be generated by using the UBRRn settings in Table 19-9. UBRRn
values which yield an actual baud rate differing less than 0.5% from the target baud rate, are
bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resis-
tance when the error ratings are high, especially for large serial frames (see “Asynchronous
Operational Range” on page 188). The error values are calculated using the following equation:
Table 19-8. UCPOLn Bit Settings
UCPOLn
Transmitted Data Changed (Output of
TxDn Pin)
Received Data Sampled (Input on RxDn
Pin)
0 Rising XCKn Edge Falling XCKn Edge
1 Falling XCKn Edge Rising XCKn Edge
Bit 151413121110 9 8
UBRRn[11:8] UBRRnH
UBRRn[7:0] UBRRnL
76543210
Read/Write R R R R R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
00000000
Error[%]
BaudRate
Closest Match
BaudRate
-------------------------------------------------- 1
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