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ATMEGA48-20AU

Part # ATMEGA48-20AU
Description MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

169
2545M–AVR–09/07
ATmega48/88/168
18.5 Register Description
18.5.1 SPCR – SPI Control Register
Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS
is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL functionality is sum-
marized below:
Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL
functionality is summarized below:
Bit 76543210
0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 18-3. CPOL Functionality
CPOL Leading Edge Trailing Edge
0 Rising Falling
1 Falling Rising
Table 18-4. CPHA Functionality
CPHA Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample
170
2545M–AVR–09/07
ATmega48/88/168
Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f
osc
is
shown in the following table:
18.5.2 SPSR – SPI Status Register
Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS
is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega48/88/168 and will always read as zero.
Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 18-5). This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
osc
/4
or lower.
The SPI interface on the ATmega48/88/168 is also used for program memory and EEPROM
downloading or uploading. See page 299 for serial programming and verification.
Table 18-5. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1 SPR0 SCK Frequency
000
f
osc
/4
001f
osc
/16
010f
osc
/64
011
f
osc
/128
100f
osc
/2
101f
osc
/8
110
f
osc
/32
111f
osc
/64
Bit 76543210
0x2D (0x4D) SPIF WCOL SPI2X SPSR
Read/Write RRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0
171
2545M–AVR–09/07
ATmega48/88/168
18.5.3 SPDR – SPI Data Register
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
Bit 76543210
0x2E (0x4E) MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial ValueXXXXXXXXUndefined
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