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ATmega48/88/168

The clock source for Timer/Counter2 is named clk

T2S

. clk

T2S

is by default connected to the main

system I/O clock clk

. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously

clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter

(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can

then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock

source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal.

For Timer/Counter2, the possible prescaled selections are: clk

T2S

/8, clk

T2S

/32, clk

T2S

/64,

clk

T2S

/128, clk

T2S

/256, and clk

T2S

/1024. Additionally, clk

T2S

as well as 0 (stop) may be selected.

Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a

predictable prescaler.

17.11 Register Description

17.11.1 TCCR2A – Timer/Counter Control Register A

• Bits 7:6 – COM2A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin

must be set in order to enable the output driver.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM22:0 bit setting. Table 17-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

Table 17-3 on page 155 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set

to fast PWM mode.

Bit 7 6 5 4 3210

(0xB0)

COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 TCCR2A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 17-2. Compare Output Mode, non-PWM Mode

COM2A1 COM2A0 Description

0 0 Normal port operation, OC2A disconnected.

0 1 Toggle OC2A on Compare Match

1 0 Clear OC2A on Compare Match

1 1 Set OC2A on Compare Match

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Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 147

for more details.

Table 17-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 149 for more details.

• Bits 5:4 – COM2B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0

bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin

must be set in order to enable the output driver.

When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the

WGM22:0 bit setting. Table 17-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

Table 17-3. Compare Output Mode, Fast PWM Mode

(1)

COM2A1 COM2A0 Description

0 0 Normal port operation, OC2A disconnected.

WGM22 = 0: Normal Port Operation, OC0A Disconnected.

WGM22 = 1: Toggle OC2A on Compare Match.

Clear OC2A on Compare Match, set OC2A at BOTTOM,

(non-inverting mode)

Set OC2A on Compare Match, clear OC2A at BOTTOM,

(inverting mode)

Table 17-4. Compare Output Mode, Phase Correct PWM Mode

(1)

COM2A1 COM2A0 Description

0 0 Normal port operation, OC2A disconnected.

WGM22 = 0: Normal Port Operation, OC2A Disconnected.

WGM22 = 1: Toggle OC2A on Compare Match.

Clear OC2A on Compare Match when up-counting. Set OC2A on

Compare Match when down-counting.

Set OC2A on Compare Match when up-counting. Clear OC2A on

Compare Match when down-counting.

Table 17-5. Compare Output Mode, non-PWM Mode

COM2B1 COM2B0 Description

0 0 Normal port operation, OC2B disconnected.

0 1 Toggle OC2B on Compare Match

1 0 Clear OC2B on Compare Match

1 1 Set OC2B on Compare Match

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Table 17-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM

mode.

Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 149 for more details.

Table 17-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 149 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bits 1:0 – WGM21:0: Waveform Generation Mode

Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 17-8. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 146).

Table 17-6. Compare Output Mode, Fast PWM Mode

(1)

COM2B1 COM2B0 Description

0 0 Normal port operation, OC2B disconnected.

01Reserved

Clear OC2B on Compare Match, set OC2B at BOTTOM,

(non-inverting mode)

Set OC2B on Compare Match, clear OC2B at BOTTOM,

(invertiing mode)

Table 17-7. Compare Output Mode, Phase Correct PWM Mode

(1)

COM2B1 COM2B0 Description

0 0 Normal port operation, OC2B disconnected.

01Reserved

Clear OC2B on Compare Match when up-counting. Set OC2B on

Compare Match when down-counting.

Set OC2B on Compare Match when up-counting. Clear OC2B on

Compare Match when down-counting.

Part #	ATMEGA48-20AU
Description	MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category	IC
Availability	Out of Stock
Qty	0

ATMEGA48-20AU

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