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17.2.1 Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg-

isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag

(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source he Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-

tive when no clock source is selected. The output from the Clock Select logic is referred to as the

timer clock (clk

The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and

OC2B). See “Output Compare Unit” on page 143. for details. The compare match event will also

set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare

interrupt request.

17.2.2 Definitions

Many register and bit references in this document are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 2. However, when using the register or bit

defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2

counter value and so on.

The definitions in Table 17-1 are also used extensively throughout the section.

17.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous

clock source. The clock source clk

is by default equal to the MCU clock, clk

I/O

. When the AS2

bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter

Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “ASSR

– Asynchronous Status Register” on page 160. For details on clock sources and prescaler, see

“Timer/Counter Prescaler” on page 153.

17.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

17-2 shows a block diagram of the counter and its surrounding environment.

Table 17-1. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR2A Register. The assignment is depen-

dent on the mode of operation.

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ATmega48/88/168

Figure 17-2. Counter Unit Block Diagram

Signal description (internal signals):

count Increment or decrement TCNT2 by 1.

direction Selects between increment and decrement.

clear Clear TCNT2 (set all bits to zero).

clk

Timer/Counter clock, referred to as clk

in the following.

top Signalizes that TCNT2 has reached maximum value.

bottom Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk

). clk

can be generated from an external or internal clock source,

selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clk

is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in

the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter

Control Register B (TCCR2B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.

For more details about advanced counting sequences and waveform generation, see “Modes of

Operation” on page 146.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by

the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.

17.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a

match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the Output Compare Flag can be cleared by software by writing a logical

one to its I/O bit location. The Waveform Generator uses the match signal to generate an output

according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0)

bits. The max and bottom signals are used by the Waveform Generator for handling the special

cases of the extreme values in some modes of operation (“Modes of Operation” on page 146).

Figure 17-3 shows a block diagram of the Output Compare unit.

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

topbottom

direction

clear

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clk

I/O

clk

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ATmega48/88/168

Figure 17-3. Output Compare Unit, Block Diagram

The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double

buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR2x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR2x directly.

17.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the

OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare

match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or

toggled).

17.5.2 Compare Match Blocking by TCNT2 Write

All CPU write operations to the TCNT2 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initial-

ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is

enabled.

17.5.3 Using the Output Compare Unit

Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,

independently of whether the Timer/Counter is running or not. If the value written to TCNT2

equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is

downcounting.

OCFnx (Int.Req.)

(8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnX1:0

bottom

Part #	ATMEGA48-20AU
Description	MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category	IC
Availability	Out of Stock
Qty	0

ATMEGA48-20AU

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