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2545M–AVR–09/07

ATmega48/88/168

Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least

one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f

ExtClk

< f

clk_I/O

/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f

clk_I/O

/2.5.

An external clock source can not be prescaled.

Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1

(1)

Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 16-1.

PSRSYNC

Clear

clk

I/O

Synchronization

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2545M–AVR–09/07

ATmega48/88/168

16.1 Register Description

16.1.1 GTCCR – General Timer/Counter Control Register

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-

ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are

halted and can be configured to the same value without the risk of one of them advancing during

configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared

by hardware, and the Timer/Counters start counting simultaneously.

• Bit 0 – PSRSYNC: Prescaler Reset

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-

mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1

and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both

timers.

Bit 765432 1 0

0x23 (0x43) TSM

– – – – – PSRASY PSRSYNC GTCCR

Read/WriteR/WRRRRRR/WR/W

Initial Value000000 0 0

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ATmega48/88/168

17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation

17.1 Features

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)

• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

17.2 Overview

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified

block diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For the actual placement of

I/O pins, refer to “Pinout ATmega48/88/1682545M” on page 2. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the “Register Description” on page 154.

The PRTIM2 bit in “Minimizing Power Consumption” on page 42 must be written to zero to

enable Timer/Counter2 module.

Figure 17-1. 8-bit Timer/Counter Block Diagram

Clock Select

Timer/Counter

DATA BUS

OCRnA

OCRnB

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Fixed

TOP

Value

Control Logic

TOP BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

TCCRnA TCCRnB

Edge

Detector

( From Prescaler )

clk

Part #	ATMEGA48-20AU
Description	MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category	IC
Availability	Out of Stock
Qty	0

ATMEGA48-20AU

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Technical Document