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15.11.7 ICR1H and ICR1L – Input Capture Register 1

The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the

ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 111.

15.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register

• Bit 7, 6 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (see “Interrupts” on page 57) is executed when the ICF1 Flag, located in TIFR1, is set.

• Bit 4, 3 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 57) is executed when the OCF1B Flag, located in

TIFR1, is set.

• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 57) is executed when the OCF1A Flag, located in

TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector

(See “Interrupts” on page 57) is executed when the TOV1 Flag, located in TIFR1, is set.

Bit 76543210

(0x87) ICR1[15:8] ICR1H

(0x86) ICR1[7:0] ICR1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0x6F) – – ICIE1 – – OCIE1B OCIE1A TOIE1 TIMSK1

Read/Write R R R/W R R R/W R/W R/W

Initial Value00000000

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ATmega48/88/168

15.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register

• Bit 7, 6 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the

counter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF1 can be cleared by writing a logic one to its bit location.

• Bit 4, 3 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-

cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-

cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 0 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,

the TOV1 Flag is set when the timer overflows. Refer to Table 15-4 on page 133 for the TOV1

Flag behavior when using another WGM13:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.

Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

Bit 76543210

0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 TIFR1

Read/Write R R R/W R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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16. Timer/Counter0 and Timer/Counter1 Prescalers

“8-bit Timer/Counter0 with PWM” on page 90 and “16-bit Timer/Counter1 with PWM” on page

109 share the same prescaler module, but the Timer/Counters can have different prescaler set-

tings. The description below applies to both Timer/Counter1 and Timer/Counter0.

16.0.1 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f

CLK_I/O

). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f

CLK_I/O

/8, f

CLK_I/O

/64, f

CLK_I/O

/256, or

CLK_I/O

/1024.

16.0.2 Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is

not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications

for situations where a prescaled clock is used. One example of prescaling artifacts occurs when

the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock

cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system

clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-

tion. However, care must be taken if the other Timer/Counter that shares the same prescaler

also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is

connected to.

16.0.3 External Clock Source

An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock

(clk

/clk

). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization

logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 16-1

shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector

logic. The registers are clocked at the positive edge of the internal system clock (

clk

I/O

). The latch

is transparent in the high period of the internal system clock.

The edge detector generates one clk

/clk

pulse for each positive (CSn2:0 = 7) or negative

(CSn2:0 = 6) edge it detects.

Figure 16-1. T1/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T1/T0 pin to the counter is updated.

Tn_sync

(To Clock

Select Logic)

Edge DetectorSynchronization

DQDQ

clk

I/O

Part #	ATMEGA48-20AU
Description	MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category	IC
Availability	Out of Stock
Qty	0

ATMEGA48-20AU

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