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Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

15.11.2 TCCR1B – Timer/Counter1 Control Register B

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is

activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four

successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture

event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied into the

Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this

can be used to cause an Input Capture Interrupt, if this interrupt is enabled.

Table 15-4. Waveform Generation Mode Bit Description

(1)

Mode WGM13

WGM12

(CTC1)

WGM11

(PWM11)

WGM10

(PWM10)

Timer/Counter Mode of

Operation TOP

Update of

OCR1x at

TOV1 Flag

Set on

0 0 0 0 0 Normal 0xFFFF Immediate MAX

1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM

2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM

3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM

4 0 1 0 0 CTC OCR1A Immediate MAX

5 0 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP

6 0 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP

7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP

81000

PWM, Phase and Frequency

Correct

ICR1 BOTTOM BOTTOM

91001

PWM, Phase and Frequency

Correct

OCR1A BOTTOM BOTTOM

10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM

11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM

12 1 1 0 0 CTC ICR1 Immediate MAX

13 1 1 0 1 (Reserved) – – –

14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP

15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP

Bit 7 6 5 4 3 2 1 0

(0x81) ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the

TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-

ture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be

written to zero when TCCR1B is written.

• Bit 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.

• Bit 2:0 – CS12:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure

15-10 and Figure 15-11.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

15.11.3 TCCR1C – Timer/Counter1 Control Register C

• Bit 7 – FOC1A: Force Output Compare for Channel A

• Bit 6 – FOC1B: Force Output Compare for Channel B

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode..

When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on

the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0

bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the

value present in the COM1x1:0 bits that determine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer

on Compare match (CTC) mode using OCR1A as TOP.

Table 15-5. Clock Select Bit Description

CS12 CS11 CS10 Description

0 0 0 No clock source (Timer/Counter stopped).

001clk

I/O

/1 (No prescaling)

010clk

I/O

/8 (From prescaler)

011clk

I/O

/64 (From prescaler)

100clk

I/O

/256 (From prescaler)

101clk

I/O

/1024 (From prescaler)

1 1 0 External clock source on T1 pin. Clock on falling edge.

1 1 1 External clock source on T1 pin. Clock on rising edge.

Bit 7 6 5 4 3 2 1 0

(0x82) FOC1A FOC1B – – – – – – TCCR1C

Read/Write R/W R/W R R R R R R

Initial Value 0 0 0 0 0 0 0 0

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2545M–AVR–09/07

ATmega48/88/168

The FOC1A/FOC1B bits are always read as zero.

15.11.4 TCNT1H and TCNT1L – Timer/Counter1

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit

Registers” on page 111.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-

pare match between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock

for all compare units.

15.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A

15.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B

The Output Compare Registers contain a 16-bit value that is continuously compared with the

counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC1x pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are

written simultaneously when the CPU writes to these registers, the access is performed using an

8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other

16-bit registers. See “Accessing 16-bit Registers” on page 111.

Bit 76543210

(0x85) TCNT1[15:8] TCNT1H

(0x84) TCNT1[7:0] TCNT1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0x89) OCR1A[15:8] OCR1AH

(0x88) OCR1A[7:0] OCR1AL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0x8B) OCR1B[15:8] OCR1BH

(0x8A) OCR1B[7:0] OCR1BL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Part #	ATMEGA48-20AU
Description	MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category	IC
Availability	Out of Stock
Qty	0

ATMEGA48-20AU

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