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ATMEGA48-20AU

Part # ATMEGA48-20AU
Description MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

46
2545M–AVR–09/07
ATmega48/88/168
10. System Control and Reset
10.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. For the ATmega168, the instruction placed at the Reset Vector must be a
JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega48 and
ATmega88, the instruction placed at the Reset Vector must be an RJMP – Relative Jump –
instruction to the reset handling routine. If the program never enables an interrupt source, the
Interrupt Vectors are not used, and regular program code can be placed at these locations. This
is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in
the Boot section or vice versa (ATmega88/168 only). The circuit diagram in Figure 10-1 shows
the reset logic. Table 28-3 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in “Clock Sources” on page 29.
10.2 Reset Sources
The ATmega48/88/168 has four sources of reset:
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
threshold (V
POT
).
External Reset. The MCU is reset when a low level is present on the RESET
pin for longer than
the minimum pulse length.
Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog System Reset mode is enabled.
Brown-out Reset. The MCU is reset when the supply voltage V
CC
is below the Brown-out Reset
threshold (V
BOT
) and the Brown-out Detector is enabled.
47
2545M–AVR–09/07
ATmega48/88/168
Figure 10-1. Reset Logic
10.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in “System and Reset Characteristics” on page 308. The POR is activated whenever
V
CC
is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
CC
rise. The RESET signal is activated again, without any delay,
when V
CC
decreases below the detection level.
Figure 10-2. MCU Start-up, RESET
Tied to V
CC
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA B U S
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
RSTDISBL
V
RESET
T
IME-OUT
I
NTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
48
2545M–AVR–09/07
ATmega48/88/168
Figure 10-3. MCU Start-up, RESET Extended Externally
10.4 External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see “System and Reset Characteristics” on page 308) will generate a
reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
When the applied signal reaches the Reset Threshold Voltage – V
RST
– on its positive edge, the
delay counter starts the MCU after the Time-out period – t
TOUT
has expired. The External Reset
can be disabled by the RSTDISBL fuse, see Table 27-6 on page 288.
Figure 10-4. External Reset During Operation
10.5 Brown-out Detection
ATmega48/88/168 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V
CC
level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can
be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free
Brown-out Detection. The hysteresis on the detection level should be interpreted as V
BOT+
=
V
BOT
+ V
HYST
/2 and V
BOT-
= V
BOT
- V
HYST
/2.When the BOD is enabled, and V
CC
decreases to a
value below the trigger level (V
BOT-
in Figure 10-5), the Brown-out Reset is immediately acti-
vated. When V
CC
increases above the trigger level (V
BOT+
in Figure 10-5), the delay counter
starts the MCU after the Time-out period t
TOUT
has expired.
The BOD circuit will only detect a drop in V
CC
if the voltage stays below the trigger level for
longer than t
BOD
given in “System and Reset Characteristics” on page 308.
RESET
T
IME-OUT
I
NTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC
CC
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