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ATMEGA48-20AU

Part # ATMEGA48-20AU
Description MCU 8BIT ATMEGA RISC 4KB FLASH 3.3V/5V 32TQFP - Trays
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

358
2545M–AVR–09/07
ATmega48/88/168
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF
before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
The only safe time to write to any of the Timer2 registers in asynchronous mode is in a com-
pare interrupt routine where the compare register is not 0xFF, or if the compare register is
0xFF, after a delay of at least one asynchronous clock cycle from the start of the interrupt.
34.1.4 Rev A
Part may hang in reset
Wrong values read after Erase Only operation
Watchdog Timer Interrupt disabled
Start-up time with Crystal Oscillator is higher than expected
High Power Consumption in Power-down with External Clock
Asynchronous Oscillator does not stop in Power-down
Interrupts may be lost when writing the timer registers in the asynchronous timer
1. Part may hang in reset
Some parts may get stuck in a reset state when a reset signal is applied when the internal
reset state-machine is in a specific state. The internal reset state-machine is in this state for
approximately 10 ns immediately before the part wakes up after a reset, and in a 10 ns win-
dow when altering the system clock prescaler. The problem is most often seen during In-
System Programming of the device. There are theoretical possibilities of this happening also
in run-mode. The following three cases can trigger the device to get stuck in a reset-state:
- Two succeeding resets are applied where the second reset occurs in the 10ns window
before the device is out of the reset-state caused by the first reset.
- A reset is applied in a 10 ns window while the system clock prescaler value is updated by
software.
- Leaving SPI-programming mode generates an internal reset signal that can trigger this
case.
The two first cases can occur during normal operating mode, while the last case occurs only
during programming of the device.
Problem Fix/Workaround
The first case can be avoided during run-mode by ensuring that only one reset source is
active. If an external reset push button is used, the reset start-up time should be selected
such that the reset line is fully debounced during the start-up time.
The second case can be avoided by not using the system clock prescaler.
The third case occurs during In-System programming only. It is most frequently seen when
using the internal RC at maximum frequency.
If the device gets stuck in the reset-state, turn power off, then on again to get the device out
of this state.
2. Wrong values read after Erase Only operation
At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only oper-
ation may read as programmed (0x00).
Problem Fix/Workaround
359
2545M–AVR–09/07
ATmega48/88/168
If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write opera-
tion with 0xFF as data in order to erase a location. In any case, the Write Only operation can
be used as intended. Thus no special considerations are needed as long as the erased loca-
tion is not read before it is programmed.
3. Watchdog Timer Interrupt disabled
If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog
will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in
interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-
out following an interrupt, the device works correctly.
Problem fix / Workaround
Make sure there is enough time to always service the first timeout event before a new
watchdog timeout occurs. This is done by selecting a long enough time-out period.
4. Start-up time with Crystal Oscillator is higher than expected
The clock counting part of the start-up time is about 2 times higher than expected for all
start-up periods when running on an external Crystal. This applies only when waking up by
reset. Wake-up from power down is not affected. For most settings, the clock counting parts
is a small fraction of the overall start-up time, and thus, the problem can be ignored. The
exception is when using a very low frequency crystal like for instance a 32 kHz clock crystal.
Problem fix / Workaround
No known workaround.
5. High Power Consumption in Power-down with External Clock
The power consumption in power down with an active external clock is about 10 times
higher than when using internal RC or external oscillators.
Problem fix / Workaround
Stop the external clock when the device is in power down.
6. Asynchronous Oscillator does not stop in Power-down
The Asynchronous oscillator does not stop when entering power down mode. This leads to
higher power consumption than expected.
Problem fix / Workaround
Manually disable the asynchronous timer before entering power down.
7. Interrupts may be lost when writing the timer registers in the asynchronous timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-
ten in the cycle before an overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF
before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
The only safe time to write to any of the Timer2 registers in asynchronous mode is in a com-
pare interrupt routine where the compare register is not 0xFF, or if the compare register is
0xFF, after a delay of at least one asynchronous clock cycle from the start of the interrupt.
360
2545M–AVR–09/07
ATmega48/88/168
34.2 Errata ATmega88
The revision letter in this section refers to the revision of the ATmega88 device.
34.2.1 Rev. D
Interrupts may be lost when writing the timer registers in the asynchronous timer
1. Interrupts may be lost when writing the timer registers in the asynchronous timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-
ten in the cycle before an overflow interrupt occurs, the interrupt may be lost.
The only safe time to write to any of the Timer2 registers in asynchronous mode is in a com-
pare interrupt routine where the compare register is not 0xFF, or if the compare register is
0xFF, after a delay of at least one asynchronous clock cycle from the start of the interrupt.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF
before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.
34.2.2 Rev. B/C
Not sampled.
34.2.3 Rev. A
Writing to EEPROM does not work at low Operating Voltages
Part may hang in reset
Interrupts may be lost when writing the timer registers in the asynchronous timer
1. Writing to EEPROM does not work at low operating voltages
Writing to the EEPROM does not work at low voltages.
Problem Fix/Workaround
Do not write the EEPROM at voltages below 4.5 Volts.
This will be corrected in rev. B.
2. Part may hang in reset
Some parts may get stuck in a reset state when a reset signal is applied when the internal
reset state-machine is in a specific state. The internal reset state-machine is in this state for
approximately 10 ns immediately before the part wakes up after a reset, and in a 10 ns win-
dow when altering the system clock prescaler. The problem is most often seen during In-
System Programming of the device. There are theoretical possibilities of this happening also
in run-mode. The following three cases can trigger the device to get stuck in a reset-state:
- Two succeeding resets are applied where the second reset occurs in the 10ns window
before the device is out of the reset-state caused by the first reset.
- A reset is applied in a 10 ns window while the system clock prescaler value is updated by
software.
- Leaving SPI-programming mode generates an internal reset signal that can trigger this
case.
The two first cases can occur during normal operating mode, while the last case occurs only
during programming of the device.
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