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AT45DB081D-SU-2.5

Part # AT45DB081D-SU-2.5
Description DATAFLASH, 8M, SERIAL, 2.5V -IND TEMP, GREEN 8 LEAD SOIC
Category IC
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Technical Document


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AT45DB081D
11. Additional Commands
11.1 Main Memory Page to Buffer Transfer
A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start
the operation for the DataFlash standard page size (264 bytes), a 1-byte opcode, 53H for buffer
1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes com-
prised of 3 don’t care bits, 12 page address bits (PA11 - PA0), which specify the page in main
memory that is to be transferred, and 9 don’t care bits. To perform a main memory page to buffer
transfer for the binary page size (256 bytes), the opcode 53H for buffer 1 or 55H for buffer 2,
must be clocked into the device followed by three address bytes consisting of 4 don’t care bits,
12 page address bits (A19 - A8) which specify the page in the main memory that is to be trans-
ferred, and 8 don’t care bits. The CS
pin must be low while toggling the SCK pin to load the
opcode and the address bytes from the input pin (SI). The transfer of the page of data from the
main memory to the buffer will begin when the CS
pin transitions from a low to a high state. Dur-
ing the transfer of a page of data (t
XFR
), the status register can be read to determine whether the
transfer has been completed.
11.2 Main Memory Page to Buffer Compare
A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate
the operation for DataFlash standard page size, a 1-byte opcode, 60H for buffer 1 and 61H for
buffer 2, must be clocked into the device, followed by three address bytes consisting of 3 don’t
care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory that is to
be compared to the buffer, and 9 don’t care bits. To start a main memory page to buffer compare
for a binary page size, the opcode 60H for buffer 1 or 61H for buffer 2, must be clocked into the
device followed by three address bytes consisting of 4 don’t care bits, 12 page address bits
(A19 - A8) that specify the page in the main memory that is to be compared to the buffer, and
8 don’t care bits. The CS
pin must be low while toggling the SCK pin to load the opcode and the
address bytes from the input pin (SI). On the low-to-high transition of the CS
pin, the data bytes
in the selected main memory page will be compared with the data bytes in buffer 1 or buffer 2.
During this time (t
COMP
), the status register will indicate that the part is busy. On completion of
the compare operation, bit 6 of the status register is updated with the result of the compare.
11.3 Auto Page Rewrite
This mode is only needed if multiple bytes within a page or multiple pages of data are modified in
a random fashion within a sector. This mode is a combination of two operations: Main Memory
Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of
data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data
(from buffer 1 or buffer 2) is programmed back into its original page of main memory. To start the
rewrite operation for the DataFlash standard page size (264 bytes), a 1-byte opcode, 58H for
buffer 1 or 59H for buffer 2, must be clocked into the device, followed by three address bytes
comprised of 3 don’t care bits, 12 page address bits (PA11-PA0) that specify the page in main
memory to be rewritten and 9 don’t care bits. To initiate an auto page rewrite for a binary page
size (256 bytes), the opcode 58H for buffer 1 or 59H for buffer 2, must be clocked into the device
followed by three address bytes consisting of 4 don’t care bits, 12 page address bits (A19 - A8)
that specify the page in the main memory that is to be written and 8 don’t care bits. When a low-
to-high transition occurs on the CS
pin, the part will first transfer data from the page in main
memory to a buffer and then program the data from the buffer back into same page of main
memory. The operation is internally self-timed and should take place in a maximum time of t
EP
.
During this time, the status register will indicate that the part is busy.
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AT45DB081D
If a sector is programmed or reprogrammed sequentially page by page, then the programming
algorithm shown in Figure 25-1 (page 45) is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sector, then the programming algorithm
shown in Figure 25-2 (page 46) is recommended. Each page within a sector must be
updated/rewritten at least once within every 10,000 cumulative page erase/program operations
in that sector.
11.4 Status Register Read
The status register can be used to determine the device’s ready/busy status, page size, a Main
Memory Page to Buffer Compare operation result, the Sector Protection status or the device
density. The Status Register can be read at any time, including during an internally self-timed
program or erase operation. To read the status register, the CS
pin must be asserted and the
opcode of D7H must be loaded into the device. After the opcode is clocked in, the 1-byte status
register will be clocked out on the output pin (SO), starting with the next clock cycle. The data in
the status register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next
eight clock cycles. After the one byte of the status register has been clocked out, the sequence
will repeat itself (as long as CS
remains low and SCK is being toggled). The data in the status
register is constantly updated, so each repeating sequence will output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is
not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. Since the data in the status register is constantly updated, the user must toggle SCK pin to
check the ready/busy status. There are several operations that can cause the device to be in a
busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program, Main Memory Page Program through Buffer, Page
Erase, Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using
bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the
data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does
not match the data in the buffer.
Bit 1 in the Status Register is used to provide information to the user whether or not the sector
protection has been enabled or disabled, either by software-controlled method or hardware-con-
trolled method. A logic 1 indicates that sector protection has been enabled and logic 0 indicates
that sector protection has been disabled.
Bit 0 in the Status Register indicates whether the page size of the main memory array is config-
ured for “power of 2” binary page size (256 bytes) or the DataFlash standard page size
(264 bytes). If bit 0 is a 1, then the page size is set to 256 bytes. If bit 0 is a 0, then the page size
is set to 264 bytes.
The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the
AT45DB081D, the four bits are 1001 The decimal value of these four binary bits does not equate
to the device density; the four bits represent a combinational code relating to differing densities
of DataFlash devices. The device density is not the same as the density code indicated in the
JEDEC device ID information. The device density is provided only for backward compatibility.
Table 11-1. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY
COMP 1 0 0 1 PROTECT PAGE SIZE
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12. Deep Power-down
After initial power-up, the device will default in standby mode. The Deep Power-down command
allows the device to enter into the lowest power consumption mode. To enter the Deep Power-
down mode, the CS
pin must first be asserted. Once the CS pin has been asserted, an opcode
of B9H command must be clocked in via input pin (SI). After the last bit of the command has
been clocked in, the CS
pin must be de-asserted to initiate the Deep Power-down operation.
After the CS
pin is de-asserted, the will device enter the Deep Power-down mode within the
maximum t
EDPD
time. Once the device has entered the Deep Power-down mode, all instructions
are ignored except for the Resume from Deep Power-down command.
Figure 12-1. Deep Power-down
12.1 Resume from Deep Power-down
The Resume from Deep Power-down command takes the device out of the Deep Power-down
mode and returns it to the normal standby mode. To Resume from Deep Power-down mode, the
CS
pin must first be asserted and an opcode of ABH command must be clocked in via input pin
(SI). After the last bit of the command has been clocked in, the CS
pin must be de-asserted to
terminate the Deep Power-down mode. After the CS
pin is de-asserted, the device will return to
the normal standby mode within the maximum t
RDPD
time. The CS pin must remain high during
the t
RDPD
time before the device can receive any commands. After resuming form Deep Power-
down, the device will return to the normal standby mode.
Figure 12-2. Resume from Deep Power-Down
Command Opcode
Deep Power-down B9H
Opcode
CS
Each transition
represents 8 bits
SI
Command Opcode
Resume from Deep Power-down ABH
Opcode
CS
Each transition
represents 8 bits
SI
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