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AT45DB081D-SU-2.5

Part # AT45DB081D-SU-2.5
Description DATAFLASH, 8M, SERIAL, 2.5V -IND TEMP, GREEN 8 LEAD SOIC
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $0.65000

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

49
3596E–DFLASH–02/07
AT45DB081D
27.2 8S2 – EIAJ SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
4/7/06
8S2 D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
θ 0° 8°
e 1.27 BSC 4
θ
θ
1
1
N
N
E
E
TOP VIEW
TOP VIEW
C
C
E1
E1
END VIEW
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
SIDE VIEW
50
3596E–DFLASH–02/07
AT45DB081D
27.3 8M1-A – MLF
2325 Orchard Parkway
San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
8M1-A, 8-pad, 6 x 5 x 1.00 mm Body, Very Thin Dual Flat Package
No Lead (MLF)
C
8M1-A
9/8/06
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
A – 0.85 1.00
A1 – – 0.05
A2 0.65 TYP
A3 0.20 TYP
b 0.35 0.40 0.48
D 5.90 6.00 6.10
D1 5.70 5.75 5.80
D2 3.20 3.40 3.60
E 4.90 5.00 5.10
E1 4.70 4.75 4.80
E2 3.80 4.00 4.20
e 1.27
L 0.50 0.60 0.75
– – 12
o
K 0.25 – –
Pin 1 ID
TOP VIEW
Pin #1 Notch
(0.20 R)
BOTTOM VIEW
D2
E2
L
b
D1
D
E1
E
e
A3
A2
A1
A
0.08
C
0
SIDE VIEW
0
K
0.45
51
3596E–DFLASH–02/07
AT45DB081D
28. Revision History
Revision Level – Release Date History
A – November 2005 Initial Release
B – March 2006
Added Preliminary.
Added text, in “Programming the Configuration Register”, to indicate
that power cycling is required to switch to “power of 2” page size
after the opcode enable has been executed.
Added “Legacy Commands” table.
C – July 2006
Corrected PA3 in opcode 50h for addressing sequence with
standard page size. Corrected Chip Erase opcode from 7CH to
C7H. Clarified the commands B and C usage for operation mode.
D – November 2006
Removed Preliminary.
Added errata regarding Chip Erase.
Changed various timing parameters under Table 18-4.
E – February 2007 Removed RDY/BUSY
pin references.
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