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AT27C512R-70JI

Part # AT27C512R-70JI
Description IC OTP 512KBIT 70NS 32PLCC
Category IC
Availability Out of Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Features
Fast Read Access Time – 45 ns
Low-Power CMOS Operation
100 µA Max Standby
20 mA Max Active at 5 MHz
JEDEC Standard Packages
28-lead PDIP
32-lead PLCC
28-lead TSOP and SOIC
5V ± 10% Supply
High-Reliability CMOS Technology
2,000V ESD Protection
200 mA Latchup Immunity
Rapid Programming Algorithm – 100 µs/Byte (Typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Industrial and Automotive Temperature Ranges
Green (Pb/Halide-free) Packaging Option
1. Description
The AT27C512R is a low-power, high-performance 524,288-bit one-time programma-
ble read-only memory (OTP EPROM) organized 64K by 8 bits. It requires only one 5V
power supply in normal read mode operation. Any byte can be accessed in less than
45 ns, eliminating the need for speed reducing WAIT states on high-performance
microprocessor systems.
Atmel’s scaled CMOS technology provides high-speed, lower active power consump-
tion, and significantly faster programming. Power consumption is typically only 8 mA
in Active Mode and less than 10 µA in Standby.
The AT27C512R is available in a choice of industry-standard JEDEC-approved one-
time programmable (OTP) plastic PDIP, PLCC, SOIC, and TSOP packages. All
devices feature two-line control (CE
, OE) to give designers the flexibility to prevent
bus contention.
With 64K byte storage capability, the AT27C512R allows firmware to be stored reli-
ably and to be accessed by the system without the delays of mass storage media.
Atmel’s AT27C512R has additional features to ensure high quality and efficient pro-
duction use. The Rapid Programming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only
100 µs/byte. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages.
512K (64K x 8)
OTP EPROM
AT27C512R
0015O–EPROM–12/07
2
0015O–EPROM–12/07
AT27C512R
2.1 28-lead PDIP/SOIC Top View
2.2 32-lead PLCC Top View
Note: PLCC Package Pins 1 and 17 are Don’t Connect.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A14
A13
A8
A9
A11
OE/VPP
A10
CE
O7
O6
O5
O4
O3
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
O0
A8
A9
A11
NC
OE/VPP
A10
CE
O7
O6
4
3
2
1
32
31
30
14
15
16
17
18
19
20
O1
O2
GND
NC
O3
O4
O5
A7
A12
A15
NC
VCC
A14
A13
2.3 28-lead TSOP Top View – Type 1
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A15
A12
A7
A6
A5
A4
A3
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A1
A2
OE/VPP
A11
A9
A8
A13
A14
VCC
1
2
3
4
5
6
7
2. Pin Configurations
Pin Name Function
A0 - A15 Addresses
O0 - O7 Outputs
CE
Chip Enable
OE
/VPP Output Enable/ Program Supply
NC No Connect
3
0015O–EPROM–12/07
AT27C512R
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce tran-
sient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high
frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the V
CC
and Ground terminals of the device, as close
to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the V
CC
and Ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
V
CC
+ 0.75V DC which may overshoot to +7.0 volts for pulses of less than 20 ns.
5. Absolute Maximum Ratings*
Temperature Under Bias............................... -55°C to + 125°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and func-
tional operation of the device at these or any other
conditions beyond those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Storage Temperature .................................... -65°C to + 150°C
Voltage on Any Pin with
Respect to Ground ........................................-2.0V to + 7.0V
(1)
Voltage on A9 with
Respect to Ground .....................................-2.0V to + 14.0V
(1)
V
PP
Supply Voltage with
Respect to Ground ......................................-2.0V to + 14.0V
(1)
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