Features

• Low-voltage and Standard-voltage Operation

– 2.7 (V

= 2.7V to 5.5V)

– 1.8 (V

= 1.8V to 3.6V)

• Internally Organized 65,536 x 8

• Two-wire Serial Interface

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• 128-byte Page Write Mode (Partial Page Writes Allowed)

• Self-timed Write Cycle (5 ms Max)

• High Reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 40 Years

• Automotive Devices Available

• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,

8-lead LAP, 8-lead SAP and 8-ball dBGA2 Packages

• Die Sales: Wafer Form, Waffle Pack and Bumped Die

Description

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable

read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s

cascadable feature allows up to four devices to share a common two-wire bus. The

device is optimized for use in many industrial and commercial applications where low-

power and low-voltage operation are essential. The devices are available in space-

saving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead

Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is avail-

able in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Table 1. Pin Configurations

Pin Name Function

A0–A1 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

Rev. 1116O–SEEPR–1/07

Two-wire Serial

EEPROM

512K (65,536 x 8)

AT24C512

Note: Not recommended for new

design; please refer to

AT24C512B datasheet.

8-lead PDIP

GND

VCC

SCL

SDA

8-lead Leadless Array

Bottom View

SCL

8-lead TSSOP

8-lead SAP

Bottom View

SCL

8-lead SOIC

GND

VCC

SCL

SDA

8-ball dBGA2

Bottom View

VCC

SCL

SDA

GND

AT24C512

1116O–SEEPR–1/07

Figure 1. Block Diagram

Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground ....................................–1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

AT24C512

1116O–SEEPR–1/07

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is

open-drain driven and may be wire-ORed with any number of other open-drain or open

collector devices.

DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are

hardwired or left not connected for hardware compatibility with other AT24Cxx devices.

When the pins are hardwired, as many as four 512K devices may be addressed on a

single bus system (device addressing is discussed in detail under the Device Address-

ing section. If the pins are left floating, the A1 and A0 pins will be internally pulled down

to GND if the capacitive coupling to the circuit board V

plane is <3 pF. If coupling is

>3 pF, Atmel recommends connecting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-

mal write operations. When WP is connected high to V

, all write operations to the

memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down

to GND if the capacitive coupling to the circuit board V

plane is <3 pF. If coupling is

>3 pF, Atmel recommends connecting the pin to GND. Switching WP to V

prior to a

write operation creates a software write protect function.

Memory Organization AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of

128-bytes each. Random word addressing requires a 16-bit data word address.

Part #	AT24C512W-10SU-2.7
Description	IC EEPROM 512KBIT 1MHZ 8SOIC
Category	IC
Availability	In Stock
Qty	2954

Qty	Price
1 - 131	$1.14341
132 - 329	$0.90953
330 - 641	$0.85756
642 - 972	$0.79692
973 +	$0.71030

AT24C512W-10SU-2.7

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Technical Document