(Features

• Low-voltage and Standard-voltage Operation

– 1.8 (V

= 1.8 to 5.5V)

• Internally Organized 4096 x 8, 8192 x 8

• 2-Wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bi-directional Data Transfer Protocol

• 1 MHz (5.0V) and 400 KHz (1.8V Compatibility)

• Write Protect Pin for Hardware Data Protection

• 32-Byte Page Write Mode (Partial Page Writes Allowed)

• Self-Timed Write Cycle (5 ms max)

• High Reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

• Lead-free/Halogen-free Devices

• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead

TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3), and 8-ball dBGA2 Packages.

• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers

Description

The AT24C32C/64C provides 32,768/65,536 bits of serial electrically erasable and

programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits

each. The device’s cascadable feature allows up to 8 devices to share a common 2-

wire bus. The device is optimized for use in many industrial and commercial applica-

tions where low power and low voltage operation are essential. The AT24C32C/64C is

available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame

Land Grid Array (ULA), 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3) and, 8-

ball dBGA2 packages and is accessed via a 2-wire serial interface. In addition, the

entire family is available in 1.8V (1.8 to 5.5V) version.

2-Wire

Serial EEPROM

32K (4096 x 8)

64K (8192 x 8)

AT24C32C

AT24C64C

5298A–SEEPR–1/08

2-Wire, 32K

Serial E

PROM

Pin Configurations

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

8-lead Ultra Thin

Mini-MAP (MLP 2x3)

GND

VCC

SCL

SDA

Bottom View

8-lead PDIP

GND

VCC

SCL

SDA

8-lead TSSOP

GND

VCC

SCL

SDA

8-lead SOIC

GND

VCC

SCL

SDA

8-ball dBGA2

GND

VCC

SCL

SDA

Bottom View

8-lead Ultra Lead Frame

Land Grid Array (ULA)

GND

VCC

SCL

SDA

Bottom View

5298A–SEEPR–1/08

AT24C32C/64C

1. Block Diagram

Absolute Maximum Ratings*

Operating Temperature...................................... -55 to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature ......................................... -65 to +150°C

Voltage on Any Pin

with Respect to Ground ....................................... -1.0 to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

START

STOP

LOGIC

VCC

GND

SCL

SDA

SERIAL

CONTROL

LOGIC

H.V. PUMP/TIMING

EEPROM

DATA RECOVERY

SERIAL MUX

X DEC

OUT

/ACK

LOGIC

COMP

LOAD

INC

DATA WO R D

ADDR/COUNTER

Y DEC

R/W

OUT

LOAD

DEVICE

ADDRESS

COMPARATOR

5298A–SEEPR–1/08

AT24C32C/64C

2. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM

device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain

driven and may be wire-ORed with any number of other open-drain or open collector devices.

DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are

hard wired or left not connected for hardware compatibility with other AT24CXX devices. When

the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus

system (device addressing is discussed in detail under the Device Addressing section). If the

pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capaci-

tive coupling to the circuit board V

plane is <3pF. If coupling is >3pF, Atmel

recommends

connecting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write

operations. When WP is connected high to V

, all write operations to the memory are inhibited.

If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive cou-

pling to the circuit board V

plane is <3pF. If coupling is >3pF, Atmel recommends connecting

the pin to GND.

Part #	AT24C32CN-SH-B
Description	IC EEPROM 32KBIT 1MHZ 8SOIC
Category	IC
Availability	In Stock
Qty	10

AT24C32CN-SH-B

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Technical Document