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AT17LV002-10TQU

Part # AT17LV002-10TQU
Description FPGA CONFIG SERIAL EEPROM, 2M, 3.3V - 10 MHZ, 3.3V, 44 TQF
Category IC
Availability In Stock
Qty 970
Qty Price
1 - 10 $24.94873
11 - 25 $19.84558
26 - 53 $18.71154
54 - 115 $17.38851
116 + $15.49845
Manufacturer Available Qty
Atmel
Date Code: 0523
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Features
EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
Supports both 3.3V and 5.0V Operating Voltage Applications
In-System Programmable (ISP) via Two-Wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera
®
FLEX
®
, APEX
Devices, ORCA
®
, Xilinx
®
XC3000, XC4000, XC5200, Spartan
®
, Virtex
®
FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP
Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
High-reliability
Endurance: 100,000 Write Cycles
Data Retention: 90 Years for Industrial Parts (at 85° C) and 190 Years for
Commercial Parts (at 70° C)
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
1. Description
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-
to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-
lead PLCC, 20-lead SOIC and 44-lead TQFP, see Table 1-1. The AT17LV series
Configurators uses a simple serial-access procedure to configure one or more FPGA
devices. The user can select the polarity of the reset function by programming four
EEPROM bytes. These devices also support a write-protection mechanism within its
programming mode.
The AT17LV series configurators can be programmed with industry-standard pro-
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
FPGA
Configuration
EEPROM
Memory
AT17LV65
AT17LV128
AT17LV256
AT17LV512
AT17LV010
AT17LV002
AT17LV040
3.3V and 5V
System Support
2321I–CNFG–2/08
2
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC
package is not available for the AT17LV512/010/002 devices, it is possible to use an 8-lead
LAP package instead.
2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the
AT17LV512/010/002 devices.
3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.
2. Pin Configuration
Figure 2-1. 8-lead LAP
Figure 2-2. 8-lead SOIC
Figure 2-3. 8-lead PDIP
Table 1-1. AT17LV Series Packages
Package
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010 AT17LV002 AT17LV040
8-lead LAP Yes Yes Yes
(3)
8-lead PDIP Yes Yes
8-lead SOIC Yes
Use 8-lead
LAP
(1)
Use 8-lead
LAP
(1)
(3)
20-lead PLCC Yes Yes Yes
20-lead SOIC Yes
(2)
Ye s
(2)
Ye s
(2)
44-lead TQFP Yes Yes
8
7
6
5
1
2
3
4
DATA
CLK
(WP
(1)
) RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
1
2
3
4
8
7
6
5
DATA
CLK
(WP
(1)
) RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
1
2
3
4
8
7
6
5
DATA
CLK
(WP
(1)
) RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
3
2321I–CNFG–2/08
AT17LV65/128/256/512/010/002/040
Figure 2-4. 20-lead PLCC
Notes: 1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
3. The CEO feature is not available on the AT17LV65 device.
Figure 2-5. 20-lead SOIC
(1)
Note: 1. This pinout only applies to AT17LV65/128/256 devices.
4
5
6
7
8
18
17
16
15
14
CLK
(WP1
(2)
) NC
(WP
(1)
) RESET/OE
(WP2
(2)
) NC
CE
NC
SER_EN
NC
NC (READY
(2)
)
CEO (A2)
3
2
1
20
19
9
10
11
12
13
NC
GND
NC
NC
NC
NC
DATA
NC
VCC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
DATA
NC
CLK
NC
RESET/OE
NC
CE
NC
GND
VCC
NC
NC
SER_EN
NC
NC
CEO (A2)
NC
NC
NC
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