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AD698SQ

Part # AD698SQ
Description Universal LVDT Signal Conditioner 24-Pin CDIP
Category IC
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1 + $94.06779



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

AD698
REV. B
–7–
b. Full-scale core displacement from null, d
S × d = VTR and also equals the ratio A/B at mechanical full
scale. The VTR should be converted to units of V/V.
For a full-scale displacement of d inches, voltage out of the
AD698 is computed as
V
OUT
= S × d × 500 µA × R2
V
OUT
is measured with respect to the signal reference,
Pin 21, shown in Figure 7.
Solving for R2,
R2 =
V
OUT
S × d × 500 µA
(1)
For V
OUT
= ±10 V full-scale range (20 V span) and d = ±0.1
inch full-scale displacement (0.2 inch span)
R2 =
20V
2.4 × 0.2 × 500 µA
= 83.3 k
V
OUT
as a function of displacement for the above example is
shown in Figure 10.
+10
+0.1d (INCHES)
–0.1
–10
V
OUT
(VOLTS)
Figure 10. V
OUT
(
±
10 V Full Scale) vs. Core Displace-
ment (
±
0.1 Inch)
E. Optional Offset of Output Voltage Swing
9. Selections of R3 and R4 permit a positive or negative output
voltage offset adjustment.
V
OS
= 1. 2 V × R 2 ×
1
R3 + 2 k
1
R
4
+ 2 k
(2)
For no offset adjustment R3 and R4 should be open circuit.
To design a circuit producing a 0 V to +10 V output for a
displacement of +0.1 inch, set V
OUT
to +10 V, d = 0.2 inch
and solve Equation (1) for R2.
+5
+0.1d (INCHES)
–0.1
–5
V
OUT
(VOLTS)
Figure 11. V
OUT
(
±
5 V Full Scale) vs. Core Displacement
(
±
0.1 Inch)
This will produce a response shown in Figure 11.
In Equation (2) set V
OS
= 5 V and solve for R3 and R4. Since a
positive offset is desired, let R4 be open circuit. Rearranging
Equation (2) and solving for R3
R3 =
1. 2 × R 2
V
OS
–2kΩ=7.02 k
Multiply the primary excitation voltage by the VTR to get
the expected secondary voltage at mechanical full scale. For
example, for an LVDT with a sensitivity of 2.4 mV/V/mil and
a full scale of ±0.1 inch, the VTR = 0.0024 V/V/Mil × 100
mil = 0.24. Assuming the maximum excitation of 3.5 V rms,
the maximum secondary voltage will be 3.5 V rms × 0.24 =
0.84 V rms, which is in the acceptable range.
Conversely the VTR may be measured explicitly. With the
LVDT energized at its typical drive level V
PRI
, as indicated
by the manufacturer, set the core displacement to its me-
chanical full-scale position and measure the output V
SEC
of
the secondary. Compute the LVDT voltage transformation
ratio, VTR. VTR = V
SEC
//VPRI. For the E100, V
SEC
= 0.72 V
for V
PRI
= 3 V. VTR = 0.24.
For situations where LVDT sensitivity is low, or the me-
chanical FS is a small fraction of the total stroke length, an
input excitation of more than 3.5 V rms may be needed. In
this case a voltage divider network may be placed across the
LVDT primary to provide smaller voltage for the +BIN and
–BIN input. If, for example, a network was added to divide
the B Channel input by 1/2, then the VTR should also be re-
duced by 1/2 for the purpose of component selection.
Check the power supply voltages by verifying that the peak
values of V
A
and V
B
are at least 2.5 volts less than the volt-
ages at +V
S
and –V
S
.
6. Referring to Figure 9, for V
S
= ±15 V, select the value of the
amplitude determining component R1 as shown by the curve
in Figure 9.
30
15
0
0.01 0.1 1k100101
5
10
20
25
V rms
R1 – k
V
EXC
– V rms
Figure 9. Excitation Voltage V
EXC
vs. R1
7. C2, C3 and C4 are a function of the desired bandwidth of
the AD698 position measurement subsystem. They should
be nominally equal values.
C2 = C3 = C4 = 10
–4
Farad Hz/f
5UBSYSTEM
(Hz)
If the desired system bandwidth is 250 Hz, then
C2 = C3 = C4 = 10
-4
Farad Hz/250 Hz = 0.4 µF
See Figures 14, 15 and 16 for more information about
AD698 bandwidth and phase characterization.
D. Set the Full-Scale Output Voltage
8. To compute R2, which sets the AD698 gain or full-scale
output range, several pieces of information are needed:
a. LVDT sensitivity, S
REV. B
–8–
AD698
Note that V
OS
should
be chosen so that R3 cannot have negative
value .
Figure 12 shows the desired response.
+5
+0.1d (INCHES)
–0.1
V
OUT
(VOLTS)
+10
Figure 12. V
OUT
(0 V–10 V Full Scale) vs. Displacement
(
±
0.1 Inch)
DESIGN PROCEDURE
SINGLE SUPPLY OPERATION
Figure 13 shows the single supply connection method.
R1
C1
C2
C3
R4
R3
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD698
–V
S
EXC1
EXC2
LEV1
LEV2
FREQ1
BFILT1
BFILT2
–BIN
+BIN
–AIN
FREQ2
SIG REF
OFFSET2
OFFSET1
+V
S
OUT FILT
FEEDBACK
SIG OUT
–ACOMP
AFILT2
AFILT1
+ACOMP
+AIN
C4
R2
1000pF
SIGNAL
REFERENCE
R
L
V
OUT
0.1µF
V
ps
+30V
6.8µF
1M
R6
R5
C5
AB
C
D
PHASE
LAG/LEAD
NETWORK
R
T
AB
CD
PHASE LEAD
R
S
C
C
R
S
R
S
R
T
A
B
CD
PHASE LAG
C
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = R
S
// (R
S
+ R
T
)
Figure 13. Interconnection Diagram for Single Supply
Operation
For single supply operation, repeat Steps 1 through 10 of the
design procedure for dual supply operation. R5, R6 and C5 are
additional component values to be determined. V
OUT
is mea-
sured with respect to SIGNAL REFERENCE.
10. Compute a maximum value of R5 and R6 based upon the
relationship
R5 + R6 V
PS
/100
µ
A
11. The voltage drop across R5 must be greater than
2 + 10 k
1. 2 V
R 4 + 2 k
+ 250 µA +
V
OUT
4 × R2
Volts
Therefore
R5
2 + 10 k
1. 2 V
R 4 + 2 k
+ 250 µA +
V
OUT
4 × R2
100 µA
Ohms
Based upon the constraints of R5 + R6 (Step 10) and R5 (Step
11), select an interim value of R6.
12. Load current through R
L
returns to the junction of R5 and
R6, and flows back to V
PS
. Under maximum load condi-
tions, make sure the voltage drop across R5 is met as de-
fined in Step 11.
As a final check on the power supply voltages, verify that
the peak values of V
A
and V
B
are at least 2.5 volts less than
the voltage between +V
S
and –V
S
.
13. C5 is a bypass capacitor in the range of 0.1 µF to 1 µF.
Gain Phase Characteristics
To use an LVDT in a closed-loop mechanical servo application,
it is necessary to know the dynamic characteristics of the trans-
ducer and interface elements. The transducer itself is very quick
to respond once the core is moved. The dynamics arise prima-
rily from the interface electronics. Figures 14, 15 and 16 show
the frequency response of the AD698 LVDT Signal Conditioner.
Note that Figures 15 and 16 are basically the same; the differ-
ence is frequency range covered. Figure 15 shows a wider range
of mechanical input frequencies at the expense of accuracy.
FREQUENCY – Hz
0 10k100 1k
10
0
–30
–60
–70
0
–10
–20
–50
–40
GAIN – dB
–360
–60
–240
–300
–420
–180
–120
PHASE SHIFT – Degrees
0.1µF
0.33µF
2.0µF
R2 = 81k
f
EXC
= 2.5kHz
0.1µF
0.33µF
2.0µF
R2 = 81k
f
EXC
= 2.5kHz
Figure 14. Gain and Phase Characteristics vs. Frequency
(0 kHz–10 kHz)
AD698
REV. B
–9–
FREQUENCY – Hz
0 100k100 1k 10k
10
0
–30
–60
–70
0
–10
–20
–50
–40
–360
–60
–240
–300
–420
–180
–120
GAIN – dB
PHASE SHIFT – Degrees
0.1µF
0.033µF
0.01µF
R2 = 81k
f
EXC
= 10kHz
0.1µF
0.033µF
0.01µF
R2 = 81k
f
EXC
= 10kHz
Figure 15. Gain and Phase Characteristics vs. Frequency
(0 kHz–50 kHz)
FREQUENCY – Hz
0 100 1k 10k
10
0
–30
–60
–70
–10
–20
–50
–40
0
–360
–60
–240
–300
–180
–120
GAIN – dB
PHASE SHIFT – Degrees
0.1µF
0.033µF
0.01µF
R2 = 81k
f
EXC
= 10kHz
0.1µF
0.033µF
0.01µF
R2 = 81k
f
EXC
= 10kHz
Figure 16. Gain and Phase Characteristics vs. Frequency
(0 kHz–10 kHz)
Figure 16 shows a more limited frequency range with enhanced
accuracy. The figures are transfer functions with the input to be
considered as a sinusoidally varying mechanical position and the
output as the voltage from the AD698; the units of the transfer
function are volts per inch. The value of C2, C3, and C4, from
Figure 7, are all equal and designated as a parameter in the fig-
ures. The response is approximately that of two real poles.
However, there is appreciable excess phase at higher frequen-
cies. An additional pole of filtering can be introduced with a
shunt capacitor across R2, Figure 7; this will also increase phase
lag.
When selecting values of C2, C3 and C4 to set the bandwidth of
the system, a trade-off is involved. There is ripple on the “dc”
position output voltage, and the magnitude is determined by the
filter capacitors. Generally, smaller capacitors will give higher
system bandwidth and larger ripple. Figures 17 and 18 show the
magnitude of ripple as a function of C2, C3 and C4, again all
equal in value. Note also a shunt capacitor across R2, Figure 7,
is shown as a parameter. The value of R2 used was 81 k with a
Schaevitz E100 LVDT.
C2, C3, C4; C2 = C3 = C4 – µF
RIPPLE – mV rms
1k
100
0.1
0.01 0.1 101
10
1
2.5kHz, C
SHUNT
1nF
2.5kHz, C
SHUNT
10nF
Figure 17. Output Voltage Ripple vs. Filter Capacitance
C2, C3, C4; C2 = C3 = C4 – µF
RIPPLE – mV rms
1k
100
0.1
0.001 0.01 100.1
10
1
10kHz, C
SHUNT
1nF
10kHz, C
SHUNT
10nF
1
Figure 18. Output Voltage Ripple vs. Filter Capacitance
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