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AD698SQ

Part # AD698SQ
Description Universal LVDT Signal Conditioner 24-Pin CDIP
Category IC
Availability Out of Stock
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1 + $94.06779



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

REV. B
–4–
AD698
Typical Characteristics
(at +25°C and V
S
= ±15 V unless otherwise noted)
240
–20
140
20
0
–40–60
80
40
120
160
200
120100806040200–20
TEMPERATURE – °C
GAIN AND OFFSET PSRR – ppm/V
OFFSET PSRR 12–15V
OFFSET PSRR 15–18V
GAIN PSRR 12–15V
GAIN PSRR 15–18V
Figure 1. Gain and Offset PSRR vs. Temperature
140–40–60 120100806040200–20
0
–45
–35
–40
–30
–25
–20
–15
–10
–05
TEMPERATURE – °C
GAIN AND OFFSET CMRR – ppm/V
OFFSET CMRR ± 3V
GAIN CMRR ± 3V
Figure 2. Gain and Offset CMRR vs. Temperature
120
–80
140
–40
–60
–40–60
0
–20
20
40
80
120100806040200–20
TEMPERATURE – °C
TYPICAL GAIN DRIFT – ppm/°C
Figure 3. Typical Gain Drift vs. Temperature
20
–20
140
–10
–15
–40–60
0
–5
5
10
15
120100806040200–20
TEMPERATURE – °C
TYPICAL OFFSET DRIFT – ppm/°C
Figure 4. Typical Offset Drift vs. Temperature
AD698
REV. B
–5–
THEORY OF OPERATION
A block diagram of the AD698 along with an LVDT (linear
variable differential transformer) connected to its input is shown
in Figure 5 below. The LVDT is an electromechanical trans-
ducer—its input is the mechanical displacement of a core, and
its output is an ac voltage proportional to core position. Two
popular types of LVDTs are the half-bridge type and the series
opposed or four-wire LVDT. In both types the moveable core
couples flux between the windings. The series-opposed con-
nected LVDT transducer consists of a primary winding ener-
gized by an external sine wave reference source and two
second
ary windings connected in the series opposed configuration.
The output voltage across the series secondary increases as the core
is moved from the center. The direction of movement is detected
by measuring the phase of the output. Half-bridge LVDTs have a
single coil with a center tap and work like an autotransformer. The
excitation voltage is applied across the coil; the voltage at the center
tap is proportional to position. The device behaves similarly to a
resistive voltage divider.
A
B
AMP
OSCILLATOR
VOLTAGE
REFERENCE
A
B
FILTER
AMP
AD698
Figure 5. Functional Block Diagram
The AD698 energizes the LVDT coil, senses the LVDT output
voltages and produces a dc output voltage proportional to core
position. The AD698 has a sine wave oscillator and power am-
plifier to drive the LVDT. Two synchronous demodulation
stages are available for decoding the primary and secondary
voltages. A decoder determines the ratio of the output signal
voltage to the input drive voltage (A/B). A filter stage and out-
put amplifier are used to scale the resulting output.
The oscillator comprises a multivibrator that produces a triwave
output. The triwave drives a sine shaper that produces a low dis-
tortion sine wave. Frequency and amplitude are determined by a
single resistor and capacitor. Output frequency can range from
20 Hz to 20 kHz and amplitude from 2 V to 24 V rms. Total har-
monic distortion is typically –50 dB.
The AD698 decodes LVDTs by synchronously demodulating
the amplitude modulated input (secondaries), A, and a fixed in-
put reference (primary or sum of secondaries or fixed input), B.
A common problem with earlier solutions was that any drift in
the amplitude of the drive oscillator corresponded directly to a
gain error in the output. The AD698, eliminates
these errors by
calculating the ratio of the LVDT output to its input excitation in
order to cancel out any drift effects. This device differs from the
AD598 LVDT signal conditioner in that it implements a different
circuit transfer function and does not require the sum of the LVDT
secondaries (A + B) to be constant with stroke length.
The AD698 block diagram is shown below. The inputs consist
of two independent synchronous demodulation channels. The B
channel is designed to monitor the drive excitation to the LVDT.
The full wave rectified output is filtered by C2 and sent to the
computational circuit. Channel A is identical except that the
comparator is pinned out separately. Since the A channel may
reach 0 V output at LVDT null, the A channel demodulator is
usually triggered by the primary voltage (B Channel). In addi-
tion, a phase compensation network may be required to add a
phase lead or lag to the A Channel to compensate for the LVDT
primary to secondary phase shift. For half-bridge circuits the
phase shift is noncritical, and the A channel voltage is large
enough to trigger the demodulator.
AD698
COMP
±1
FILTER
B
CHANNEL
–BIN
+BIN
DUTY CYCLE
DIVIDER
A/B = 1 = 100%
DUTY
±1
–ACOMP
+ACOMP
–AIN
+AIN
FILTER
DEMODULATOR
A
CHANNEL
A
B
OFF 2
OFF 1
BFILT1
BFILT2
C2
V
OUT
IREF
500µA
V
OUT
FILTER
C4
FB
R2
C5
+V
S
–V
S
AFILT2AFILT1
C3
V/I
COMP
V/I
Figure 6. AD698 Block Diagram
Once both channels are demodulated and filtered a division cir-
cuit, implemented with a duty cycle multiplier, is used to calcu-
late the ratio A/B. The output of the divider is a duty cycle.
When A/B is equal to 1, the duty cycle will be equal to 100%.
(This signal can be used as is if a pulse width modulated output
is required.) The duty cycle drives a circuit that modulates and
filters a reference current proportional to the duty cycle. The
output amplifier scales the 500 µA reference current converting
it to a voltage. The output transfer function is thus:
V
OUT
= I
REF
× A/B × R2, where I
REF
= 500 µA
REV. B
–6–
AD698
CONNECTING THE AD698
The AD698 can easily be connected for dual or single supply
operation as shown in Figures 7, 8 and 13. The following gen-
eral design procedures demonstrate how external component
values are selected and can be used for any LVDT that meets
AD698 input/output criteria. The connections for the A and B
channels and the A channel comparators will depend on which
transducer is used. In general follow the guidelines below.
Parameters set with external passive components include: exci-
tation frequency and amplitude, AD698 input signal frequency,
and the scale factor (V/inch). Additionally, there are optional
features; offset null adjustment, filtering, and signal integration,
which can be implemented by adding external components.
R1
C1
15nF
C2
C3
R4
R3
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD698
–V
S
EXC1
EXC2
LEV1
LEV2
FREQ1
BFILT1
BFILT2
–BIN
+BIN
–AIN
FREQ2
SIG REF
OFFSET2
OFFSET1
+V
S
OUT FILT
FEEDBACK
SIG OUT
–ACOMP
AFILT2
AFILT1
+ACOMP
+AIN
C4
R2
33k
1000pF
SIGNAL
REFERENCE
R
L
V
OUT
100nF
6.8µF
–15V
+15V
100nF
6.8µF
Figure 7. Interconnection Diagram for Half-Bridge LVDT
and Dual Supply Operation
DESIGN PROCEDURE
DUAL SUPPLY OPERATION
Figure 7 shows the connection method for half-bridge LVDTs.
Figure 8 demonstrates the connections for 3- and 4-wire
LVDTs connected in the series opposed configuration. Both ex-
amples use dual ±15 volt power supplies.
A. Determine the Oscillator Frequency
Frequency is often determined by the required BW of the sys-
tem. However, in some systems the frequency is set to match
the LVDT zero phase frequency as recommended by the
manufacturer; in this case skip to Step 4.
1. Determine the mechanical bandwidth required for LVDT
position measurement subsystem, f
SUBSYSTEM
. For this ex-
ample, assume f
SUBSYSTEM
= 250 Hz.
2. Select minimum LVDT excitation frequency approximately
10 × f
SUBSYSTEM
. Therefore, let excitation frequency = 2.5 kHz.
3. Select a suitable LVDT that will operate with an excitation
frequency of 2.5 kHz. The Schaevitz E100, for instance, will
operate over a range of 50 Hz to 10 kHz and is an eligible
candidate for this example.
4. Select excitation frequency determining component C1.
C1 = 35 µFHz/f
EXCITATION
R1
C1
C2
C3
R4
R3
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD698
–V
S
EXC1
EXC2
LEV1
LEV2
FREQ1
BFILT1
BFILT2
–BIN
+BIN
–AIN
FREQ2
SIG REF
OFFSET2
OFFSET1
+V
S
OUT FILT
FEEDBACK
SIG OUT
–ACOMP
AFILT2
AFILT1
+ACOMP
+AIN
C4
R2
1000pF
SIGNAL
REFERENCE
R
L
V
OUT
100nF
6.8µF
–15V
+15V
100nF
6.8µF
1M
AB
C
D
PHASE
LAG/LEAD
NETWORK
R
T
AB
CD
PHASE LEAD
R
S
C
C
R
S
R
S
R
T
A
B
CD
PHASE LAG
C
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = R
S
// (R
S
+ R
T
)
Figure 8. AD698 Interconnection Diagram for Series
Opposed LVDT and Dual Supply Operation
B. Determine the Oscillator Amplitude
Amplitude is set such that the primary signal is in the 1.0 V to
3.5 V rms range and the secondary signal is in the 0.25 V to
3.5 V rms range when the LVDT is at its mechanical full-scale
position. This optimizes linearity and minimizes noise suscepti-
bility. Since the part is ratiometric, the exact value of the excita-
tion is relatively unimportant.
5. Determine optimum LVDT excitation voltage, V
EXC
. For a
4-wire LVDT determine the voltage transformation ratio,
VTR, of the LVDT at its mechanical full scale. VTR =
LVDT sensitivity × Maximum Stroke Length from null.
LVDT sensitivity is listed in the LVDT manufacturer’s cata-
log and has units of volts output per volts input per inch dis-
placement. The E100 has a sensitivity of 2.4 mV/V/mil. In
the event that LVDT sensitivity is not given by the manufac-
turer, it can be computed. See section on determining LVDT
sensitivity.
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