Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

AM85C30-10PC

Part # AM85C30-10PC
Description IC, CONTROLLER, CMOS, 40PINDIP
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $13.17267



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Publication# 10216 Rev. F Amendment/0
Issue Date: June 1993
Advanced
Micro
Devices
Am85C30
Enhanced Serial Communications Controller
FINAL
DISTINCTIVE CHARACTERISTICS
Fastest data rate of any Am8530
8.192 MHz / 2.048 Mb/s
10 MHz / 2.5 Mb/s
16.384 MHz / 4.096 Mb/s
Low-power CMOS technology
Pin and function compatible with other NMOS
and CMOS 8530s
Easily interfaced with most CPUs
Compatible with non-multiplexed bus
Many enhancements over NMOS Am8530H
Allows Am85C30 to be used more effectively in
high-speed applications
Improves interface capabilities
Two independent full-duplex serial channels
Asynchronous mode features
Programmable stop bits, clock factor, character
length and parity
Break detection/generation
Error detection for framing, overrun, and parity
Synchronous mode features
Supports IBM
BISYNC, SDLC, SDLC Loop,
HDLC, and ADCCP Protocols
Programmable CRC generators and checkers
SDLC/HDLC support includes frame control,
zero insertion and deletion, abort, and residue
handling
Enhanced SCC functions support high-speed
frame reception using DMA
14-bit byte counter
10 × 19 SDLC/HDLC Frame Status FIFO
Independent Control on both channels
Enhanced operation does not allow special
receive conditions to lock the 3-byte DATA
FIFO when the 10 × 19 FIFO is enabled
Local Loopback and Auto Echo modes
Internal or external character synchronization
2-Mb/s FM encoding transmit and receive
capability using internal DPLL for 16.384-MHz
product
Internal synchronization between RxC to PCLK
and TxC to PCLK
This allows the user to eliminate external syn-
chronization hardware required by the NMOS
device when transmitting or receiving data at
the maximum rate of 1/4 PCLK frequency
GENERAL DESCRIPTION
AMD’s Am85C30 is an enhanced pin-compatible ver-
sion of the popular Am8530H Serial Communications
Controller. The Enhanced Serial Communications
Controller (ESCC) is a high-speed, low-power, multi-
protocol communications peripheral designed for use
with 8- and 16-bit microprocessors. It has two independ-
ent,full-duplex channels and functions as a serial-to-
parallel, parallel-to-serial converter/controller. AMD’s
proprietary enhancements make the Am85C30 easier
to interface and more effective in high-speed applica-
tions due to a reduction in software burden and the elimi-
nation of the need for some external glue logic.
The Am85C30 is easy to use due to a variety of sophisti-
cated internal functions, including on-chip baud rate
generators, digital phase-locked loops, and crystal
oscillators, which dramatically reduce the need for ex-
ternal logic. The device can generate and check CRC
codes in any SYNC mode, and can be programmed to
check data integrity in various modes. The ESCC also
has facilities for modem controls in both channels. In ap-
plications where these controls are not needed, the mo-
dem controls can be used for general-purpose I/O.
This versatile device supports virtually any serial data
transfer application such as networks, modems, cas-
settes, and tape drivers. The ESCC is designed for non-
multiplexed buses and is easily interfaced with most
CPUs, such as 80188, 80186, 80286, 8080, Z80, 6800,
68000 and MULTIBUS.
AMD
2 Am85C30
Enhancements that allow the Am85C30 to be used
more effectively in high-speed applications include:
A 10 × 19 bit SDLC/HDLC frame status FIFO array
A 14-bit SDLC/HDLC frame byte counter
Automatic SDLC/HDLC opening frame flag
transmission
TxD pin forced High in SDLC NRZI mode after
closing flag
Automatic SDLC/HDLC Tx underrun/EOM flag
reset
Automatic SDLC/HDLC Tx CRC generator reset/
preset
RTS synchronization to closing SDLC/HDLC flag
DTR/REQ deactivation delay significantly reduced
External PCLK to RxC or TxC synchronization
requirement eliminated for PCLK divide-by-four
operation
Other enhancements to improve the Am85C30 inter-
face capabilities include:
Write data valid setup time to falling edge of WR
requirement eliminated
Reduced INT response time
Reduced access recovery time (t
RC
) to 3 PCLK
best case (3 1/2 PCLK worst case)
Improved Wait timing
Write Registers WR3, WR4, WR5, and WR10
made readable
Lower priority interrupt masking without INTACK
Complete SDLC/HDLC CRC character reception
BLOCK DIAGRAM
Data
Control
CPU
Bus VO
Internal
Control
Logic
Internal Bus
Channel
A
Registers
Interrupt
Control
Logic
Channel
B
Registers
+5 V GND PCLK
Channel A
Channel B
Control
Logic
Transmitter
Receiver
Baud
Rate
Generator
10×19 Bit
Frame
Status
FIFO
Interrupt
Control Lines
5
10216F-1
8
TxDA
RxDA
RTxCA
TRxCA
DTR/REQA
SYNCA
W/REQA
RTSA
CTSA
DCDA
TxDB
RxDB
RTxCB
TRxCB
DTR/REQB
SYNCB
W/REQB
RTSB
CTSB
DCDB
RELATED AMD PRODUCTS
Part No. Description Part No. Description
Am7960 Coded Data Transceiver Am9517A DMA Controller
80186 Highly Integrated 16-Bit 5380, 53C80 SCSI Bus Controller
Microprocessor 80188 Highly Integrated 8-Bit
80286, 80C286 High-Performance 16-Bit Microprocessor
Microprocessor Am386
High-Performance 32-Bit
Microprocessor
AMD
3Am85C30
CONNECTION DIAGRAMS
Top View
D
0
D
2
D
4
D
6
RD
WR
A/B
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Am85C30
10216F-2 10216F-3
Note:
Pin 1 is marked for orientation.
DIP
D
1
D
3
D
5
D
7
INT
IEO
IEI
INTACK
+5 V
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
DTR/REQA
RTSA
CTSA
DCDA
PCLK
CE
D/C
GND
W/REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
DTR/REQB
RTSB
CTSB
DCDB
1
44
43
42
5
4
3
2
641
40
7
8
9
10
11
12
13
14
15
16
17
23
24
25
26
19
20
21
22
18 27
28
39
38
37
36
35
34
33
32
31
30
29
IEO
IEI
INTACK
+5 V
W/REQA
SYNCA
RTxCA
RxDA
TRxCA
TxDA
NC
A/B
CE
D/C
NC
GND
W/REQB
SYNCB
RTxCB
RxDB
TRxCB
TxDB
INT
D
7
D
5
D
3
D
1
D
0
D2
D4
D
6
RD
WR
NC
DTR/REQA
RTSA
CTSA
DCDA
PCLK
DCDB
CTSB
RTSB
DTR/REQB
NC
PLCC, LCC
LOGIC SYMBOL
D
7
–D
0
RD
WR
A/B
CE
D/C
TxDA
RxDA
TRxCA
RTxCA
SYNCA
W/REQA
DTR/REQA
RTSA
CTSA
DCDA
TxDB
RxDB
TRxCB
RTxCB
Serial
Data
Channel
Clocks
Channel
Controls
for
Modem,
DMA, or
Other
Serial
Data
Channel
Clocks
Data
Bus
Control
+5 V GND PCLK
8
Channel
Controls
for
Modem,
DMA, or
Other
Bus Timing
and Reset
Interrupt
10216F-4
SYNCB
W/REQB
DTR/REQB
RTSB
CTSB
DCDB
INT
INTACK
IEI
IE0
1234567NEXT