Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

A3P250-FGG144

Part # A3P250-FGG144
Description IC FPGA 97 I/O 144FBGA
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $15.25371



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ProASIC3 DC and Switching Characteristics
v1.3 2-5
Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not
the ambient temperature. This is an important distinction because dynamic and static power
consumption cause the chip junction to be higher than the ambient temperature.
EQ 2-1 can be used to calculate junction temperature.
T
J
= Junction Temperature = T + T
A
EQ 2-1
where:
T
A
= Ambient Temperature
T = Temperature gradient between junction (silicon) and ambient T = θ
ja
* P
θ
ja
= Junction-to-ambient of the package. θ
ja
numbers are located in Table 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θ
jc
and the junction-to-ambient air thermal
resistivity is θ
ja
. The thermal characteristics for θ
ja
are shown for two air flow rates. The absolute
maximum junction temperature is 100°C. EQ 2-2 shows a sample calculation of the absolute
maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and
in still air.
EQ 2-2
Maximum Power Allowed
Max. junction temp. (° C) Max. ambient temp. (° C)
θ
ja
(° C/W)
-----------------------------------------------------------------------------------------------------------------------------------------
100° C70° C
20.5° C/W
-------------------------------------- 1 . 4 6 3 W
·
===
Table 2-5 • Package Thermal Resistivities
Package Type Device Pin Count θ
jc
θ
ja
UnitsStill Air 200 ft./min. 500 ft./min.
Quad Flat No Lead A3P030 132 0.4 21.4 16.8 15.3 C/W
A3P060 132 0.3 21.2 16.6 15.0 C/W
A3P125 132 0.2 21.1 16.5 14.9 C/W
A3P250 132 0.1 21.0 16.4 14.8 C/W
Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W
Thin Quad Flat Pack (TQFP) All devices 144 11.0 33.5 28.0 25.7 C/W
Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W
PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W
Fine Pitch Ball Grid Array (FBGA) See note* 144 3.8 26.9 22.9 21.5 C/W
See note* 256 3.8 26.6 22.8 21.5 C/W
See note* 484 3.2 20.5 17.0 15.9 C/W
A3P1000 144 6.3 31.6 26.2 24.2 C/W
A3P1000 256 6.6 28.1 24.4 22.7 C/W
A3P1000 484 8.0 23.3 19.0 16.7 C/W
* This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal
information will be available in future revisions of the datasheet.
ProASIC3 DC and Switching Characteristics
2-6 v1.3
Temperature and Voltage Derating Factors
Calculating Power Dissipation
Quiescent Supply Current
Power per I/O Pin
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to T
J
= 70°C, V
CC
= 1.425 V)
Array Voltage V
CC
(V)
Junction Temperature (°C)
–40°C 0°C 25°C 70°C 85°C 110°C
1.425 0.87 0.92 0.95 1.00 1.02 1.05
1.500 0.83 0.88 0.90 0.95 0.97 0.99
1.575 0.80 0.85 0.87 0.92 0.93 0.96
Table 2-7 • Quiescent Supply Current Characteristics
A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
Typical (25°C) 2 mA 2 mA 2 mA 2 mA 3 mA 3 mA 5 mA 8 mA
Max. (Commercial) 10 mA 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA 50 mA
Max. (Industrial) 15 mA 15 mA 15 mA 15 mA 30 mA 30 mA 45 mA 75 mA
Notes:
1. I
DD
Includes V
CC
, V
PUMP
, V
CCI
, and VMV currents. Values do not include I/O static contribution,
which is shown in Table 2-11 and Table 2-12 on page 2-8.
2. –F speed grade devices may experience higher standby I
DD
of up to five times the standard I
DD
and higher I/O leakage.
Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Advanced I/O Banks
VMV (V)
Static Power
P
DC2
(mW)
1
Dynamic Power P
AC9
(µW/MHz)
2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.69
2.5 V LVCMOS 2.5 5.12
1.8 V LVCMOS 1.8 2.13
1.5 V LVCMOS (JESD8-11) 1.5 1.45
3.3 V PCI 3.3 18.11
3.3 V PCI-X 3.3 18.11
Differential
LVDS 2.5 2.26 1.20
LVPECL 3.3 5.72 1.87
Notes:
1. P
DC2
is the static power (where applicable) measured on VMV.
2. P
AC9
is the total dynamic power measured on V
CC
and VMV.
ProASIC3 DC and Switching Characteristics
v1.3 2-7
Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
VMV (V)
Static Power
P
DC2
(mW)
1
Dynamic Power
P
AC9
(µW/MHz)
2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.72
2.5 V LVCMOS 2.5 5.14
1.8 V LVCMOS 1.8 2.13
1.5 V LVCMOS (JESD8-11) 1.5 1.48
3.3 V PCI 3.3 18.13
3.3 V PCI-X 3.3 18.13
Notes:
1. P
DC2
is the static power (where applicable) measured on VMV.
2. P
AC9
is the total dynamic power measured on V
CC
and VMV.
Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard I/O Banks
VMV (V)
Static Power
P
DC2
(mW)
1
Dynamic Power
P
AC9
(µW/MHz)
2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.79
2.5 V LVCMOS 2.5 5.19
1.8 V LVCMOS 1.8 2.18
1.5 V LVCMOS (JESD8-11) 1.5 1.52
Notes:
1. P
DC2
is the static power (where applicable) measured on VMV.
1. P
AC9
is the total dynamic power measured on V
CC
and VMV.
PREVIOUS12345678910111213NEXT