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A3P250-FGG144

Part # A3P250-FGG144
Description IC FPGA 97 I/O 144FBGA
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ProASIC3 DC and Switching Characteristics
2-104 v1.3
Part Number and Revision Date
Part Number 51700097-002-3
Revised August 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version Changes in Current Version (v1.3) Page
v1.2
(June 2008)
TJ, Maximum Junction Temperature, was changed to 100° from 110º in the
"Thermal Characteristics" section and EQ 2-2. The calculated result of Maximum
Power Allowed has thus changed to 1.463 W from 1.951 W.
2-5
Values for the A3P015 device were added to Table 2-7 · Quiescent Supply
Current Characteristics.
2-6
Values for the A3P015 device were added to Table 2-14 · Different Components
Contributing to Dynamic Power Consumption in ProASIC3 Devices. P
AC14
was
removed. Table 2-15 · Different Components Contributing to the Static Power
Consumption in ProASIC3 Devices is new.
2-10,
2-11
The "PLL Contribution—PPLL" section was updated to change the P
PLL
formula
from P
AC13
+ P
AC14
* F
CLKOUT
to P
DC4
+ P
AC13
* F
CLKOUT
.
2-13
Both fall and rise values were included for t
DDRISUD
and t
DDRIHD
in
Table 2-93 · Input DDR Propagation Delays.
2-71
Table 2-98 · A3P015 Global Resource is new. 2-79
The typical value for Delay Increments in Programmable Delay Blocks was
changed from 160 to 200 in Table 2-106 · ProASIC3 CCC/PLL Specification.
2-83
v1.1
(January 2008)
Table note references were added to Table 2-2 · Recommended Operating
Conditions
1
, and the order of the table notes was changed.
2-2
The title for Table 2-4 · Overshoot and Undershoot Limits
1
was modified to
remove "as measured on quiet I/Os." Table note 1 was revised to remove
"estimated SSO density over cycles." Table note 2 was revised to remove "refers
only to overshoot/undershoot limits for simultaneous switching I/Os.
"
2-3
The "Power per I/O Pin" section was updated to include 3 additional tables
pertaining to input buffer power and output buffer power.
2-6
Table 2-29 · I/O Output Buffer Maximum Resistances
1
was revised to include
values for 3.3 V PCI/PCI-X.
2-24
Table 2-81 · LVDS Minimum and Maximum DC Input and Output Levels was
updated.
2-59
v1.0
(January 2008)
In Table 2-2 · Recommended Operating Conditions
1
, T
J
was listed in the symbol
column and was incorrect. It was corrected and changed to T
A
.
2-2
In Table 2-3 · Flash Programming Limits – Retention, Storage and Operating
Temperature1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
2-2
The "PLL Behavior at Brownout Condition" section is new. 2-3
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency.
2-13
In Table 2-21 · Summary of Maximum and Minimum DC Input Levels, the note
was incorrect. It previously said T
J
and it was corrected and changed to T
A
.
2-20
ProASIC3 DC and Switching Characteristics
v1.3 2-105
v1.0
(continued)
In Table 2-106 · ProASIC3 CCC/PLL Specification, the SCLK parameter and note 1
are new.
2-83
Table 2-116 · JTAG 1532 was populated with the parameter data, which was not
in the previous version of the document.
2-103
v2.2
(July 2007)
This document was previously in datasheet v2.2. As a result of moving to the
handbook format, Actel restarted the version numbers so the new version
number is v1.0.
N/A
v2.1
(May 2007)
The T
J
parameter in Table 3-2 Recommended Operating Conditions was
changed to T
A
, ambient temperature, and table notes 4–6 were added.
3-2
v2.0
(April 2007)
Table 3-5 Package Thermal Resistivities was updated with A3P1000
information. The note below the table is also new.
3-5
Advance v0.7
(January 2007)
The timing characteristics tables were updated. N/A
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
2-15
The "PLL Macro" section was updated to include power-up information. 2-15
Table 2-11 ProASIC3 CCC/PLL Specification was updated. 2-29
Figure 2-19 Peak-to-Peak Jitter Definition is new. 2-18
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
2-21
The "RESET" section was updated with read and write information. 2-25
The "RESET" section was updated with read and write information. 2-25
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
2-28
PCI-X 3.3 V was added to Table 2-11 VCCI Voltages and Compatible Standards. 2-29
In the Table 2-15 Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
2-34
Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3
Devices was updated.
2-64
Notes 3, 4, and 5 were added to Table 2-17 Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
2-40
The "VCCPLF PLL Supply Voltage" section was updated. 2-50
The "VPUMP Programming Supply Voltage" section was updated. 2-50
The "GL Globals" section was updated to include information about direct input
into quadrant clocks.
2-51
V
JTAG
was deleted from the "TCK Test Clock" section. 2-51
In Table 2-22 Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
2-51
Ambient was deleted from Table 3-2 • Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
3-2
Note 3 is new in Table 3-4 Overshoot and Undershoot Limits (as measured on
quiet I/Os)1.
3-2
Previous Version Changes in Current Version (v1.3) Page
ProASIC3 DC and Switching Characteristics
2-106 v1.3
Advance v0.7
(continued)
In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951. 3-5
Table 3-6 Temperature and Voltage Derating Factors for Timing Delays was
updated.
3-6
Table 3-5 Package Thermal Resistivities was updated. 3-5
Table 3-14 Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
(Advanced) and Table 3-17 Summary of Maximum and Minimum DC Input
Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were
updated.
3-17 to
3-17
Table 3-20 Summary of I/O Timing Characteristics—Software Default Settings
(Advanced) and Table 3-21 Summary of I/O Timing Characteristics—Software
Default Settings (Standard Plus) were updated.
3-20 to
3-20
Table 3-11 Different Components Contributing to Dynamic Power
Consumption in ProASIC3 Devices was updated.
3-9
Table 3-24 I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3-
25 I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.
3-22 to
3-22
Table 3-17 Summary of Maximum and Minimum DC Input Levels Applicable to
Commercial and Industrial Conditions was updated.
3-18
Table 3-28 I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 I/O
Short Currents IOSH/IOSL (Standard Plus) were updated.
3-24 to
3-26
The note in Table 3-32 I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-27
Figure 3-33 Write Access After Write onto Same Address, Figure 3-34 Read
Access After Write onto Same Address, and Figure 3-35 Write Access After
Read onto Same Address are new.
3-82 to
3-84
Figure 3-43 Timing Diagram was updated. 3-96
Advance v0.5
(January 2006)
B-LVDS and M-LDVS are new I/O standards added to the datasheet. N/A
The term flow-through was changed to pass-through. N/A
Figure 2-7 Efficient Long-Line Resources was updated. 2-7
The footnotes in Figure 2-15 Clock Input Sources Including CLKBUF,
CLKBUF_LVDS/LVPECL, and CLKINT were updated.
2-16
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 ProASIC3E CCC Options.
2-24
The "SRAM and FIFO" section was updated. 2-21
The "RESET" section was updated. 2-25
The "WCLK and RCLK" section was updated. 2-25
The "RESET" section was updated. 2-25
The "RESET" section was updated. 2-27
The "Introduction" of the "Advanced I/Os" section was updated. 2-28
Previous Version Changes in Current Version (v1.3) Page
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