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A3P250-FGG144

Part # A3P250-FGG144
Description IC FPGA 97 I/O 144FBGA
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $15.25371

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ProASIC3 DC and Switching Characteristics
2-80 v1.3
Table 2-100 • A3P060 Global Resource
Commercial-Case Conditions: T
J
= 70°C, V
CC
= 1.425 V
Parameter Description
–2 –1 Std. –F
UnitsMin.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
t
RCKL
Input LOW Delay for Global Clock 0.71 0.93 0.81 1.05 0.95 1.24 1.14 1.49 ns
t
RCKH
Input HIGH Delay for Global Clock 0.700.960.801.090.941.281.131.54 ns
t
RCKMPWH
Minimum Pulse Width HIGH for Global Clock ns
t
RCKMPWL
Minimum Pulse Width LOW for Global Clock ns
t
RCKSW
Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns
F
RMAX
Maximum Frequency for Global Clock MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-101 • A3P125 Global Resource
Commercial-Case Conditions: T
J
= 70°C, V
CC
= 1.425 V
Parameter Description
–2 –1 Std. –F
UnitsMin.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
t
RCKL
Input LOW Delay for Global Clock 0.77 0.99 0.87 1.12 1.03 1.32 1.24 1.58 ns
t
RCKH
Input HIGH Delay for Global Clock 0.761.020.871.161.021.371.231.64 ns
t
RCKMPWH
Minimum Pulse Width HIGH for Global Clock ns
t
RCKMPWL
Minimum Pulse Width LOW for Global Clock ns
t
RCKSW
Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns
F
RMAX
Maximum Frequency for Global Clock MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
ProASIC3 DC and Switching Characteristics
v1.3 2-81
Table 2-102 • A3P250 Global Resource
Commercial-Case Conditions: T
J
= 70°C, V
CC
= 1.425 V
Parameter Description
–2 –1 Std. –F
UnitsMin.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
t
RCKL
Input LOW Delay for Global Clock 0.80 1.01 0.91 1.15 1.07 1.36 1.28 1.63 ns
t
RCKH
Input HIGH Delay for Global Clock 0.781.040.891.181.041.391.251.66 ns
t
RCKMPWH
Minimum Pulse Width HIGH for Global Clock ns
t
RCKMPWL
Minimum Pulse Width LOW for Global Clock ns
t
RCKSW
Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns
F
RMAX
Maximum Frequency for Global Clock MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-103 • A3P400 Global Resource
Commercial-Case Conditions: T
J
= 70°C, V
CC
= 1.425 V
Parameter Description
–2 –1 Std. –F
UnitsMin.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
t
RCKL
Input LOW Delay for Global Clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns
t
RCKH
Input HIGH Delay for Global Clock 0.861.110.981.271.151.491.381.79 ns
t
RCKMPWH
Minimum Pulse Width HIGH for Global Clock ns
t
RCKMPWL
Minimum Pulse Width LOW for Global Clock ns
t
RCKSW
Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns
F
RMAX
Maximum Frequency for Global Clock Mhz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
ProASIC3 DC and Switching Characteristics
2-82 v1.3
Table 2-104 • A3P600 Global Resource
Commercial-Case Conditions: T
J
= 70°C, V
CC
= 1.425 V
Parameter Description
–2 –1 Std. –F
UnitsMin.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
t
RCKL
Input LOW Delay for Global Clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns
t
RCKH
Input HIGH Delay for Global Clock 0.861.110.981.271.151.491.381.79 ns
t
RCKMPWH
Minimum Pulse Width HIGH for Global Clock ns
t
RCKMPWL
Minimum Pulse Width LOW for Global Clock ns
t
RCKSW
Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns
F
RMAX
Maximum Frequency for Global Clock MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-105 • A3P1000 Global Resource
Commercial-Case Conditions: T
J
= 70°C, V
CC
= 1.425 V
Parameter Description
–2 –1 Std. –F
UnitsMin.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
Min.
1
Max.
2
t
RCKL
Input LOW Delay for Global Clock 0.94 1.16 1.07 1.32 1.26 1.55 1.51 1.86 ns
t
RCKH
Input HIGH Delay for Global Clock 0.931.191.061.351.241.591.491.91 ns
t
RCKMPWH
Minimum Pulse Width HIGH for Global Clock ns
t
RCKMPWL
Minimum Pulse Width LOW for Global Clock ns
t
RCKSW
Maximum Skew for Global Clock 0.26 0.29 0.35 0.41 ns
F
RMAX
Maximum Frequency for Global Clock MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
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