ProASIC3 DC and Switching Characteristics
v1.3 2-71
Timing Characteristics
Figure 2-20 • Input DDR Timing Diagram
t
DDRICLR2Q2
t
DDRIREMCLR
t
DDRIRECCLR
t
DDRICLR2Q1
12 3 4 5 6 7 8 9
CLK
Data
CLR
Out_QR
Out_QF
t
DDRICLKQ1
2
4
6
3
5
7
t
DDRIHD
t
DDRISUD
t
DDRICLKQ2
Table 2-93 • Input DDR Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst Case V
CC
= 1.425 V
Parameter Description –2 –1 Std. –F Units
t
DDRICLKQ1
Clock-to-Out Out_QR for Input DDR 0.27 0.31 0.37 0.44 ns
t
DDRICLKQ2
Clock-to-Out Out_QF for Input DDR 0.39 0.44 0.52 0.62 ns
t
DDRISUD
Data Setup for Input DDR (Fall) 0.25 0.28 0.33 0.40 ns
Data Setup for Input DDR (Rise) 0.25 0.28 0.33 0.40 ns
t
DDRIHD
Data Hold for Input DDR (Fall) 0.00 0.00 0.00 0.00 ns
Data Hold for Input DDR (Rise) 0.00 0.00 0.00 0.00 ns
t
DDRICLR2Q1
Asynchronous Clear-to-Out Out_QR for Input DDR 0.46 0.53 0.62 0.74 ns
t
DDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR 0.57 0.65 0.76 0.92 ns
t
DDRIREMCLR
Asynchronous Clear Removal time for Input DDR 0.00 0.00 0.00 0.00 ns
t
DDRIRECCLR
Asynchronous Clear Recovery time for Input DDR 0.22 0.25 0.30 0.36 ns
t
DDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 0.36 ns
t
DDRICKMPWH
Clock Minimum Pulse Width High for Input DDR 0.36 0.41 0.48 0.57 ns
t
DDRICKMPWL
Clock Minimum Pulse Width Low for Input DDR 0.32 0.37 0.43 0.52 ns
F
DDRIMAX
Maximum Frequency for Input DDR MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating
values.
