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A3P250-FGG144

Part # A3P250-FGG144
Description IC FPGA 97 I/O 144FBGA
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $15.25371

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ProASIC3 DC and Switching Characteristics
v1.3 2-65
Table 2-88 • Parameter Definition and Measuring Nodes
Parameter Name Parameter Definition
Measuring Nodes
(from, to)*
t
OCLKQ
Clock-to-Q of the Output Data Register HH, DOUT
t
OSUD
Data Setup Time for the Output Data Register FF, HH
t
OHD
Data Hold Time for the Output Data Register FF, HH
t
OSUE
Enable Setup Time for the Output Data Register GG, HH
t
OHE
Enable Hold Time for the Output Data Register GG, HH
t
OCLR2Q
Asynchronous Clear-to-Q of the Output Data Register LL, DOUT
t
OREMCLR
Asynchronous Clear Removal Time for the Output Data Register LL, HH
t
ORECCLR
Asynchronous Clear Recovery Time for the Output Data Register LL, HH
t
OECLKQ
Clock-to-Q of the Output Enable Register HH, EOUT
t
OESUD
Data Setup Time for the Output Enable Register JJ, HH
t
OEHD
Data Hold Time for the Output Enable Register JJ, HH
t
OESUE
Enable Setup Time for the Output Enable Register KK, HH
t
OEHE
Enable Hold Time for the Output Enable Register KK, HH
t
OECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register II, EOUT
t
OEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register II, HH
t
OERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register II, HH
t
ICLKQ
Clock-to-Q of the Input Data Register AA, EE
t
ISUD
Data Setup Time for the Input Data Register CC, AA
t
IHD
Data Hold Time for the Input Data Register CC, AA
t
ISUE
Enable Setup Time for the Input Data Register BB, AA
t
IHE
Enable Hold Time for the Input Data Register BB, AA
t
ICLR2Q
Asynchronous Clear-to-Q of the Input Data Register DD, EE
t
IREMCLR
Asynchronous Clear Removal Time for the Input Data Register DD, AA
t
IRECCLR
Asynchronous Clear Recovery Time for the Input Data Register DD, AA
* See Figure 2-15 on page 2-64 for more information.
ProASIC3 DC and Switching Characteristics
2-66 v1.3
Input Register
Timing Characteristics
Figure 2-16 • Input Register Timing Diagram
50%
Preset
Clear
Out_1
CLK
Data
Enable
t
ISUE
50%
50%
t
ISUD
t
IHD
50%
50%
t
ICLKQ
1
0
t
IHE
t
IRECPRE
t
IREMPRE
t
IRECCLR
t
IREMCLR
t
IWCLR
t
IWPRE
t
IPRE2Q
t
ICLR2Q
t
ICKMPWH
t
ICKMPWL
50%
50%
50%
50%
50%
50% 50%
50%
50%
50% 50%
50%
50%
50%
Table 2-89 • Input Data Register Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case V
CC
= 1.425 V
Parameter Description –2 –1 Std. –F Units
t
ICLKQ
Clock-to-Q of the Input Data Register 0.24 0.27 0.32 0.38 ns
t
ISUD
Data Setup Time for the Input Data Register 0.26 0.30 0.35 0.42 ns
t
IHD
Data Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns
t
ISUE
Enable Setup Time for the Input Data Register 0.37 0.42 0.50 0.60 ns
t
IHE
Enable Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns
t
ICLR2Q
Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns
t
IPRE2Q
Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns
t
IREMCLR
Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns
t
IRECCLR
Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns
t
IREMPRE
Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns
t
IRECPRE
Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns
t
IWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 0.36 ns
t
IWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 0.36 ns
t
ICKMPWH
Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 0.57 ns
t
ICKMPWL
Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 0.52 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
ProASIC3 DC and Switching Characteristics
v1.3 2-67
Output Register
Timing Characteristics
Figure 2-17 • Output Register Timing Diagram
Preset
Clear
DOUT
CLK
Data_out
Enable
t
OSUE
50%
50%
t
OSUD
t
OHD
50%
50%
t
OCLKQ
1
0
t
OHE
t
ORECPRE
t
OREMPRE
t
ORECCLR
t
OREMCLR
t
OWCLR
t
OWPRE
t
OPRE2Q
t
OCLR2Q
t
OCKMPWH
t
OCKMPWL
50%
50%
50%
50%
50%
50% 50%
50%
50%
50% 50%
50%
50%
50%
50%
Table 2-90 • Output Data Register Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case V
CC
= 1.425 V
Parameter Description –2 –1 Std. –F Units
t
OCLKQ
Clock-to-Q of the Output Data Register 0.59 0.67 0.79 0.95 ns
t
OSUD
Data Setup Time for the Output Data Register 0.31 0.36 0.42 0.50 ns
t
OHD
Data Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns
t
OSUE
Enable Setup Time for the Output Data Register 0.44 0.50 0.59 0.70 ns
t
OHE
Enable Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns
t
OCLR2Q
Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns
t
OPRE2Q
Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns
t
OREMCLR
Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns
t
ORECCLR
Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns
t
OREMPRE
Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns
t
ORECPRE
Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns
t
OWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data
Register
0.22 0.25 0.30 0.36 ns
t
OWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data
Register
0.22 0.25 0.30 0.36 ns
t
OCKMPWH
Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 0.57 ns
t
OCKMPWL
Clock Minimum Pulse Width LOW for the Output Data Register 0.32 0.37 0.43 0.52 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
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