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A3P250-FGG144

Part # A3P250-FGG144
Description IC FPGA 97 I/O 144FBGA
Category IC
Availability Out of Stock
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Qty Price
1 + $15.25371



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ProASIC3 DC and Switching Characteristics
2-62 v1.3
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous
Preset
Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
INBUF
INBUF
INBUF
TRIBUF
CLKBUF
INBUF
INBUF
CLKBUF
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
Pad Out
CLK
Enable
Preset
Data_out
Data
EOUT
DOUT
Enable
CLK
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
D_Enable
A
B
C
D
E
E
E
E
F
G
H
I
J
L
K
Y
Core
Array
ProASIC3 DC and Switching Characteristics
v1.3 2-63
Table 2-87 • Parameter Definition and Measuring Nodes
Parameter Name Parameter Definition
Measuring Nodes
(from, to)*
t
OCLKQ
Clock-to-Q of the Output Data Register H, DOUT
t
OSUD
Data Setup Time for the Output Data Register F, H
t
OHD
Data Hold Time for the Output Data Register F, H
t
OSUE
Enable Setup Time for the Output Data Register G, H
t
OHE
Enable Hold Time for the Output Data Register G, H
t
OPRE2Q
Asynchronous Preset-to-Q of the Output Data Register L, DOUT
t
OREMPRE
Asynchronous Preset Removal Time for the Output Data Register L, H
t
ORECPRE
Asynchronous Preset Recovery Time for the Output Data Register L, H
t
OECLKQ
Clock-to-Q of the Output Enable Register H, EOUT
t
OESUD
Data Setup Time for the Output Enable Register J, H
t
OEHD
Data Hold Time for the Output Enable Register J, H
t
OESUE
Enable Setup Time for the Output Enable Register K, H
t
OEHE
Enable Hold Time for the Output Enable Register K, H
t
OEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register I, EOUT
t
OEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register I, H
t
OERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register I, H
t
ICLKQ
Clock-to-Q of the Input Data Register A, E
t
ISUD
Data Setup Time for the Input Data Register C, A
t
IHD
Data Hold Time for the Input Data Register C, A
t
ISUE
Enable Setup Time for the Input Data Register B, A
t
IHE
Enable Hold Time for the Input Data Register B, A
t
IPRE2Q
Asynchronous Preset-to-Q of the Input Data Register D, E
t
IREMPRE
Asynchronous Preset Removal Time for the Input Data Register D, A
t
IRECPRE
Asynchronous Preset Recovery Time for the Input Data Register D, A
* See Figure 2-14 on page 2-62 for more information.
ProASIC3 DC and Switching Characteristics
2-64 v1.3
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous
Clear
Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Enable
CLK
Pad Out
CLK
Enable
CLR
Data_out
Data
Y
AA
EOUT
DOUT
Core
Array
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
D_Enable
BB
CC
DD
EE
FF
GG
LL
HH
JJ
KK
CLKBUF
INBUF
INBUF
TRIBUF
INBUF
INBUF
CLKBUF
INBUF
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
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