ProASIC3 DC and Switching Characteristics
v1.3 2-61
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It
requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It
also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
Figure 2-13. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVDS implementation
because the output standard specifications are different.
Timing Characteristics
Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-84 • Minimum and Maximum DC Input and Output Levels
DC Parameter Description Min. Max. Min. Max. Min. Max. Units
V
CCI
Supply Voltage 3.0 3.3 3.6 V
V
OL
Output LOW Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V
V
OH
Output HIGH Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V
V
IL
, V
IH
Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V
V
ODIFF
Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V
V
OCM
Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V
V
ICM
Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V
V
IDIFF
Input Differential Voltage 300 300 300 mV
Table 2-85 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V) Input HIGH (V) Measuring Point* (V)
1.64 1.94 Cross point
* Measuring point = V
trip.
See Table 2-22 on page 2-20 for a complete table of trip points.
187 W
100 Ω
Z
0
= 50 Ω
Z
0
= 50 Ω
100 Ω
100 Ω
+
–
P
N
P
N
INBUF_LVPECL
OUTBUF_LVPECL
FPGA
FPGA
Bourns Part Number: CAT16-PC4F12
Table 2-86 • LVPECL
Commercial-Case Conditions: T
J
= 70°C, Worst-Case V
CC
= 1.425 V, Worst-Case V
CCI
= 3.0 V
Speed Grade t
DOUT
t
DP
t
DIN
t
PY
Units
–F 0.79 2.16 0.05 1.69 ns
Std. 0.66 1.80 0.04 1.40 ns
–1 0.56 1.53 0.04 1.19 ns
–2 0.49 1.34 0.03 1.05 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
