ProASIC3 DC and Switching Characteristics

2-56 v1.3

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI

Bus applications.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable

path characterization are described in Figure 2-10.

Table 2-75 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T

= 70°C, Worst-Case V

= 1.425 V, Worst-Case V

CCI

= 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade t

DOUT

DIN

EOUT

Units

2 mA –F 0.79 9.18 0.05 1.70 0.51 7.58 9.18 2.94 2.94 ns

Std. 0.66 7.65 0.04 1.42 0.43 6.31 7.65 2.45 2.45 ns

–1 0.56 6.50 0.04 1.21 0.36 5.37 6.50 2.08 2.08 ns

–2 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-76 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T

= 70°C, Worst-Case V

= 1.425 V, Worst-Case V

CCI

= 3.0 V

Applicable to Standard I/O Banks

Drive

Strength

Speed

Grade t

DOUT

DIN

EOUT

Units

2 mA –F 0.79 14.81 0.05 1.70 0.51 14.17 14.81 2.94 2.79 ns

Std. 0.66 12.33 0.04 1.42 0.43 11.79 12.33 2.45 2.32 ns

–1 0.56 10.49 0.04 1.21 0.36 10.03 10.49 2.08 1.98 ns

–2 0.49 9.21 0.03 1.06 0.32 8.81 9.21 1.83 1.73 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-77 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X V

OSL

OSH

Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA

Max, mA

µA

Per PCI specification Per PCI curves 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-10 • AC Loading

Test Point

Enable Path

R to V for t /t /t

CCI LZ ZL ZLS

10 pF for t /t /t /t

ZH ZHS ZLSZL

5 pF for t

R to GND for t /t /t

HZ ZH ZH

R = 1 k

Test Point

Datapath

R = 25

R to V

CCI

for t

(F)

R to GND for t

(R)

ProASIC3 DC and Switching Characteristics

v1.3 2-57

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is

described in Table 2-78.

Timing Characteristics

Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) C

LOAD

(pF)

0 3.3 0.285 * V

CCI

for t

DP(R)

0.615 * V

CCI

for t

DP(F)

* Measuring point = V

trip.

See Table 2-22 on page 2-20 for a complete table of trip points.

Table 2-79 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T

= 70°C, Worst-Case V

= 1.425 V, Worst-Case V

CCI

= 3.0 V

Applicable to Advanced I/O Banks

Speed Grade t

DOUT

DIN

EOUT

ZLS

ZHS

Units

–F 0.79 3.22 0.05 1.04 0.51 3.28 2.34 3.86 4.30 5.97 5.03 ns

Std. 0.66 2.68 0.04 0.86 0.43 2.73 1.95 3.21 3.58 4.97 4.19 ns

–1 0.56 2.28 0.04 0.73 0.36 2.32 1.66 2.73 3.05 4.22 3.56 ns

–2 0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

Table 2-80 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T

= 70°C, Worst-Case V

= 1.425 V, Worst-Case V

CCI

= 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade t

DOUT

DIN

EOUT

ZLS

ZHS

Units

–F 0.79 2.77 0.05 1.02 0.51 2.82 2.05 3.35 3.87 5.51 4.73 ns

Std. 0.66 2.31 0.04 0.85 0.43 2.35 1.70 2.79 3.22 4.59 3.94 ns

–1 0.56 1.96 0.04 0.72 0.36 2.00 1.45 2.37 2.74 3.90 3.35 ns

–2 0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating

values.

ProASIC3 DC and Switching Characteristics

2-58 v1.3

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Actel Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-11. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation

140 Ω

100 Ω

= 50 Ω

165 Ω

–

INBUF_LVDS

OUTBUF_LVDS

FPGA FPGA

Bourns Part Number: CAT16-LV4F12

Part #	A3P250-FGG144
Description	IC FPGA 97 I/O 144FBGA
Category	IC
Availability	Out of Stock
Qty	0

A3P250-FGG144

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